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Reverting r281719, this is causing buildbot failures and timeouts again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281722 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -12434,24 +12434,6 @@ SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
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bool isSigned = (Opcode == ISD::SDIVREM);
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EVT VT = Op->getValueType(0);
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Type *Ty = VT.getTypeForEVT(*DAG.getContext());
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SDLoc dl(Op);
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// If the target has hardware divide, use divide + multiply + subtract:
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// div = a / b
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// rem = a - b * div
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// return {div, rem}
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// This should be lowered into UDIV/SDIV + MLS later on.
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if (Subtarget->hasDivide()) {
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unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
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const SDValue Dividend = Op->getOperand(0);
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const SDValue Divisor = Op->getOperand(1);
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SDValue Div = DAG.getNode(DivOpcode, dl, VT, Dividend, Divisor);
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SDValue Mul = DAG.getNode(ISD::MUL, dl, VT, Div, Divisor);
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SDValue Rem = DAG.getNode(ISD::SUB, dl, VT, Dividend, Mul);
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SDValue Values[2] = {Div, Rem};
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return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VT, VT), Values);
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}
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RTLIB::Libcall LC = getDivRemLibcall(Op.getNode(),
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VT.getSimpleVT().SimpleTy);
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@ -12465,6 +12447,7 @@ SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
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Type *RetTy = (Type*)StructType::get(Ty, Ty, nullptr);
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SDLoc dl(Op);
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TargetLowering::CallLoweringInfo CLI(DAG);
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CLI.setDebugLoc(dl).setChain(InChain)
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.setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
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@ -3,12 +3,7 @@
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; expanded to a sequence of umull, lsrs, muls and sub instructions, but
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; just a call to __aeabi_uidivmod.
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;
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; When the processor features hardware division, UDIV + UREM can be turned
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; into UDIV + MLS. This prevents the library function __aeabi_uidivmod to be
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; pulled into the binary. The test uses ARMv7-M.
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;
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; RUN: llc -mtriple=armv7a-eabi -mattr=-neon -verify-machineinstrs %s -o - | FileCheck %s
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; RUN: llc -mtriple=thumbv7m-eabi -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=V7M
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv7m-arm-none-eabi"
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@ -33,16 +28,11 @@ entry:
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ret i32 %div
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}
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; Test for unsigned remainder
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define i32 @foo3() local_unnamed_addr #0 {
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entry:
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; CHECK-LABEL: foo3:
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; CHECK: __aeabi_uidivmod
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; CHECK-NOT: umull
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; V7M-LABEL: foo3:
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; V7M: udiv [[R2:r[0-9]+]], [[R0:r[0-9]+]], [[R1:r[0-9]+]]
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; V7M: mls {{r[0-9]+}}, [[R2]], [[R1]], [[R0]]
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; V7M-NOT: __aeabi_uidivmod
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%call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)()
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%rem = urem i32 %call, 1000000
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%cmp = icmp eq i32 %rem, 0
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@ -50,39 +40,6 @@ entry:
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ret i32 %conv
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}
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; Test for signed remainder
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define i32 @foo4() local_unnamed_addr #0 {
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entry:
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; CHECK-LABEL: foo4:
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; CHECK:__aeabi_idivmod
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; V7M-LABEL: foo4:
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; V7M: sdiv [[R2:r[0-9]+]], [[R0:r[0-9]+]], [[R1:r[0-9]+]]
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; V7M: mls {{r[0-9]+}}, [[R2]], [[R1]], [[R0]]
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; V7M-NOT: __aeabi_idivmod
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%call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)()
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%rem = srem i32 %call, 1000000
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ret i32 %rem
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}
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; Check that doing a sdiv+srem has the same effect as only the srem,
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; as the division needs to be computed anyway in order to calculate
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; the remainder (i.e. make sure we don't end up with two divisions).
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define i32 @foo5() local_unnamed_addr #0 {
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entry:
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; CHECK-LABEL: foo5:
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; CHECK:__aeabi_idivmod
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; V7M-LABEL: foo5:
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; V7M: sdiv [[R2:r[0-9]+]], [[R0:r[0-9]+]], [[R1:r[0-9]+]]
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; V7M-NOT: sdiv
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; V7M: mls {{r[0-9]+}}, [[R2]], [[R1]], [[R0]]
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; V7M-NOT: __aeabi_idivmod
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%call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)()
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%div = sdiv i32 %call, 1000000
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%rem = srem i32 %call, 1000000
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%add = add i32 %div, %rem
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ret i32 %add
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}
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declare i32 @GetValue(...) local_unnamed_addr
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attributes #0 = { minsize nounwind optsize }
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