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Revert "[AMDGPU] Disassembler: print label names in branch instructions"
This reverts commit 6c6dbe6252.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282396 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sam Kolton
parent
6c6dbe6252
commit
ecba0242f4
@ -28,7 +28,6 @@
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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@ -49,18 +48,6 @@ addOperand(MCInst &Inst, const MCOperand& Opnd) {
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MCDisassembler::SoftFail;
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}
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static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
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APInt SignedOffset(18, Imm * 4, true);
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int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
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if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
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return MCDisassembler::Success;
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return addOperand(Inst, MCOperand::createImm(Imm));
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}
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#define DECODE_OPERAND2(RegClass, DecName) \
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static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \
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unsigned Imm, \
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@ -444,50 +431,6 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
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return errOperand(Val, "unknown operand encoding " + Twine(Val));
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}
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//===----------------------------------------------------------------------===//
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// AMDGPUSymbolizer
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//===----------------------------------------------------------------------===//
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// Try to find symbol name for specified label
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bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
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raw_ostream &/*cStream*/, int64_t Value,
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uint64_t /*Address*/, bool IsBranch,
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uint64_t /*Offset*/, uint64_t /*InstSize*/) {
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typedef std::tuple<uint64_t, StringRef, uint8_t> SymbolInfoTy;
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typedef std::vector<SymbolInfoTy> SectionSymbolsTy;
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if (!IsBranch) {
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return false;
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}
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auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
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auto Result = std::find_if(Symbols->begin(), Symbols->end(),
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[Value](const SymbolInfoTy& Val) {
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return std::get<0>(Val) == static_cast<uint64_t>(Value)
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&& std::get<2>(Val) == ELF::STT_NOTYPE;
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});
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if (Result != Symbols->end()) {
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auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
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const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
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Inst.addOperand(MCOperand::createExpr(Add));
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return true;
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}
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return false;
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}
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//===----------------------------------------------------------------------===//
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// Initialization
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//===----------------------------------------------------------------------===//
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static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
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LLVMOpInfoCallback /*GetOpInfo*/,
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LLVMSymbolLookupCallback /*SymbolLookUp*/,
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void *DisInfo,
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MCContext *Ctx,
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std::unique_ptr<MCRelocationInfo> &&RelInfo) {
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return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
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}
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static MCDisassembler *createAMDGPUDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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@ -496,5 +439,4 @@ static MCDisassembler *createAMDGPUDisassembler(const Target &T,
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extern "C" void LLVMInitializeAMDGPUDisassembler() {
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TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler);
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TargetRegistry::RegisterMCSymbolizer(TheGCNTarget, createAMDGPUSymbolizer);
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}
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@ -18,107 +18,76 @@
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCDisassembler/MCSymbolizer.h"
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namespace llvm {
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class MCContext;
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class MCInst;
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class MCOperand;
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class MCSubtargetInfo;
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class Twine;
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class MCContext;
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class MCInst;
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class MCOperand;
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class MCSubtargetInfo;
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class Twine;
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//===----------------------------------------------------------------------===//
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// AMDGPUDisassembler
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//===----------------------------------------------------------------------===//
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class AMDGPUDisassembler : public MCDisassembler {
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private:
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mutable ArrayRef<uint8_t> Bytes;
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class AMDGPUDisassembler : public MCDisassembler {
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private:
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mutable ArrayRef<uint8_t> Bytes;
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public:
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AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
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MCDisassembler(STI, Ctx) {}
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public:
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AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
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MCDisassembler(STI, Ctx) {}
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~AMDGPUDisassembler() {}
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~AMDGPUDisassembler() {}
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DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &WS, raw_ostream &CS) const override;
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DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &WS, raw_ostream &CS) const override;
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const char* getRegClassName(unsigned RegClassID) const;
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const char* getRegClassName(unsigned RegClassID) const;
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MCOperand createRegOperand(unsigned int RegId) const;
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MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
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MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
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MCOperand createRegOperand(unsigned int RegId) const;
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MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
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MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
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MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
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MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
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DecodeStatus tryDecodeInst(const uint8_t* Table,
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MCInst &MI,
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uint64_t Inst,
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uint64_t Address) const;
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DecodeStatus tryDecodeInst(const uint8_t* Table,
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MCInst &MI,
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uint64_t Inst,
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uint64_t Address) const;
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MCOperand decodeOperand_VGPR_32(unsigned Val) const;
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MCOperand decodeOperand_VS_32(unsigned Val) const;
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MCOperand decodeOperand_VS_64(unsigned Val) const;
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MCOperand decodeOperand_VGPR_32(unsigned Val) const;
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MCOperand decodeOperand_VS_32(unsigned Val) const;
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MCOperand decodeOperand_VS_64(unsigned Val) const;
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MCOperand decodeOperand_VReg_64(unsigned Val) const;
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MCOperand decodeOperand_VReg_96(unsigned Val) const;
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MCOperand decodeOperand_VReg_128(unsigned Val) const;
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MCOperand decodeOperand_VReg_64(unsigned Val) const;
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MCOperand decodeOperand_VReg_96(unsigned Val) const;
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MCOperand decodeOperand_VReg_128(unsigned Val) const;
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MCOperand decodeOperand_SReg_32(unsigned Val) const;
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MCOperand decodeOperand_SReg_32_XM0(unsigned Val) const;
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MCOperand decodeOperand_SReg_64(unsigned Val) const;
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MCOperand decodeOperand_SReg_128(unsigned Val) const;
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MCOperand decodeOperand_SReg_256(unsigned Val) const;
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MCOperand decodeOperand_SReg_512(unsigned Val) const;
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MCOperand decodeOperand_SReg_32(unsigned Val) const;
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MCOperand decodeOperand_SReg_32_XM0(unsigned Val) const;
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MCOperand decodeOperand_SReg_64(unsigned Val) const;
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MCOperand decodeOperand_SReg_128(unsigned Val) const;
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MCOperand decodeOperand_SReg_256(unsigned Val) const;
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MCOperand decodeOperand_SReg_512(unsigned Val) const;
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enum OpWidthTy {
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OPW32,
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OPW64,
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OPW128,
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OPW_LAST_,
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OPW_FIRST_ = OPW32
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};
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unsigned getVgprClassId(const OpWidthTy Width) const;
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unsigned getSgprClassId(const OpWidthTy Width) const;
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unsigned getTtmpClassId(const OpWidthTy Width) const;
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enum OpWidthTy {
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OPW32,
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OPW64,
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OPW128,
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OPW_LAST_,
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OPW_FIRST_ = OPW32
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static MCOperand decodeIntImmed(unsigned Imm);
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static MCOperand decodeFPImmed(bool Is32, unsigned Imm);
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MCOperand decodeLiteralConstant() const;
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MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
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MCOperand decodeSpecialReg32(unsigned Val) const;
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MCOperand decodeSpecialReg64(unsigned Val) const;
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};
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unsigned getVgprClassId(const OpWidthTy Width) const;
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unsigned getSgprClassId(const OpWidthTy Width) const;
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unsigned getTtmpClassId(const OpWidthTy Width) const;
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static MCOperand decodeIntImmed(unsigned Imm);
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static MCOperand decodeFPImmed(bool Is32, unsigned Imm);
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MCOperand decodeLiteralConstant() const;
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MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
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MCOperand decodeSpecialReg32(unsigned Val) const;
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MCOperand decodeSpecialReg64(unsigned Val) const;
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};
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//===----------------------------------------------------------------------===//
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// AMDGPUSymbolizer
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//===----------------------------------------------------------------------===//
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class AMDGPUSymbolizer : public MCSymbolizer {
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private:
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void *DisInfo;
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public:
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AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
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void *disInfo)
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: MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
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bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
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int64_t Value, uint64_t Address,
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bool IsBranch, uint64_t Offset,
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uint64_t InstSize) override;
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void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
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int64_t Value,
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uint64_t Address) override {
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assert(false && "Implement if needed");
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}
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};
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} // namespace llvm
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#endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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@ -291,7 +291,6 @@ def SoppBrTarget : AsmOperandClass {
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def sopp_brtarget : Operand<OtherVT> {
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let EncoderMethod = "getSOPPBrEncoding";
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let DecoderMethod = "decodeSoppBrTarget";
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let OperandType = "OPERAND_PCREL";
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let ParserMatchClass = SoppBrTarget;
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}
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@ -6,19 +6,19 @@ s_branch loop_start
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// VI: s_branch loop_start ; encoding: [A,A,0x82,0xbf]
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// VI-NEXT: ; fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br
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// BIN: loop_start:
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// BIN-NEXT: s_branch loop_start // 000000000000: BF82FFFF
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// BIN-NEXT: BF82FFFF
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s_branch loop_end
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// VI: s_branch loop_end ; encoding: [A,A,0x82,0xbf]
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// VI-NEXT: ; fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br
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// BIN: s_branch loop_end // 000000000004: BF820000
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// BIN: BF820000
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// BIN: loop_end:
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loop_end:
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s_branch gds
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// VI: s_branch gds ; encoding: [A,A,0x82,0xbf]
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// VI-NEXT: ; fixup A - offset: 0, value: gds, kind: fixup_si_sopp_br
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// BIN: s_branch gds // 000000000008: BF820000
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// BIN: BF820000
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// BIN: gds:
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gds:
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s_nop 0
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@ -1228,18 +1228,6 @@ static void DisassembleObject(const ObjectFile *Obj, bool InlineRelocs) {
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std::sort(DataMappingSymsAddr.begin(), DataMappingSymsAddr.end());
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std::sort(TextMappingSymsAddr.begin(), TextMappingSymsAddr.end());
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if (Obj->isELF() && Obj->getArch() == Triple::amdgcn) {
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// AMDGPU disassembler uses symbolizer for printing labels
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std::unique_ptr<MCRelocationInfo> RelInfo(
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TheTarget->createMCRelocationInfo(TripleName, Ctx));
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if (RelInfo) {
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std::unique_ptr<MCSymbolizer> Symbolizer(
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TheTarget->createMCSymbolizer(
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TripleName, nullptr, nullptr, &Symbols, &Ctx, std::move(RelInfo)));
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DisAsm->setSymbolizer(std::move(Symbolizer));
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}
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}
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// Make a list of all the relocations for this section.
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std::vector<RelocationRef> Rels;
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if (InlineRelocs) {
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