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Compress SimpleValueType lists by sharing.

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Many register classes have the same value types. Share the table space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153764 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-03-30 17:42:04 +00:00
parent 8f36b0b139
commit ecf2d9fc0d
2 changed files with 17 additions and 22 deletions
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33
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -264,6 +264,10 @@ static void printRegister(raw_ostream &OS, const CodeGenRegister *Reg) {
OS << getQualifiedName(Reg->TheDef); OS << getQualifiedName(Reg->TheDef);
} }
static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
OS << getEnumName(VT);
}
// //
// runMCDesc - Print out MC register descriptions. // runMCDesc - Print out MC register descriptions.
// //
@ -547,25 +551,14 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
AllocatableRegs.insert(Order.begin(), Order.end()); AllocatableRegs.insert(Order.begin(), Order.end());
} }
OS << "namespace { // Register classes...\n"; // Build a shared array of value types.
SequenceToOffsetTable<std::vector<MVT::SimpleValueType> > VTSeqs;
// Emit the ValueType arrays for each RegisterClass for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { VTSeqs.add(RegisterClasses[rc]->VTs);
const CodeGenRegisterClass &RC = *RegisterClasses[rc]; VTSeqs.layout();
OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
// Give the register class a legal C name if it's anonymous. VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
std::string Name = RC.getName() + "VTs"; OS << "};\n";
// Emit the register list now.
OS << " // " << Name
<< " Register Class Value Types...\n"
<< " const MVT::SimpleValueType " << Name
<< "[] = {\n ";
for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
OS << getEnumName(RC.VTs[i]) << ", ";
OS << "MVT::Other\n };\n\n";
}
OS << "} // end anonymous namespace\n\n";
// Now that all of the structs have been emitted, emit the instances. // Now that all of the structs have been emitted, emit the instances.
if (!RegisterClasses.empty()) { if (!RegisterClasses.empty()) {
@ -692,7 +685,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
<< RegisterClasses[i]->getName() << "RegClass = {\n " << RegisterClasses[i]->getName() << "RegClass = {\n "
<< '&' << Target.getName() << "MCRegisterClasses[" << RC.getName() << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
<< "RegClassID],\n " << "RegClassID],\n "
<< RC.getName() << "VTs,\n " << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n "
<< RC.getName() << "SubclassMask,\n "; << RC.getName() << "SubclassMask,\n ";
if (RC.getSuperClasses().empty()) if (RC.getSuperClasses().empty())
OS << "NullRegClasses,\n "; OS << "NullRegClasses,\n ";

6
utils/TableGen/SequenceToOffsetTable.h
View File

@ -103,7 +103,9 @@ public:
/// emit - Print out the table as the body of an array initializer. /// emit - Print out the table as the body of an array initializer.
/// Use the Print function to print elements. /// Use the Print function to print elements.
void emit(raw_ostream &OS, void (*Print)(raw_ostream&, ElemT)) const { void emit(raw_ostream &OS,
void (*Print)(raw_ostream&, ElemT),
const char *Term = "0") const {
assert(Entries && "Call layout() before emit()"); assert(Entries && "Call layout() before emit()");
for (typename SeqMap::const_iterator I = Seqs.begin(), E = Seqs.end(); for (typename SeqMap::const_iterator I = Seqs.begin(), E = Seqs.end();
I != E; ++I) { I != E; ++I) {
@ -113,7 +115,7 @@ public:
Print(OS, *SI); Print(OS, *SI);
OS << ", "; OS << ", ";
} }
OS << "0,\n"; OS << Term << ",\n";
} }
} }
}; };