mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-12 06:06:19 +00:00
Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass.
INSERT_SUBREG will now only appear in SSA machine instructions. Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant since partial redef COPY instructions appear. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107726 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
fca3a25fed
commit
ed2185e171
@ -265,7 +265,7 @@ bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
|
||||
if (MO.getReg() == Reg && MO.isDef()) {
|
||||
assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
|
||||
MI.getOperand(MOIdx).getSubReg() &&
|
||||
MO.getSubReg());
|
||||
(MO.getSubReg() || MO.isImplicit()));
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
@ -117,10 +117,24 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
|
||||
}
|
||||
}
|
||||
|
||||
// Eliminate %reg1032:sub<def> = COPY undef.
|
||||
if (MI->isCopy() && MI->getOperand(0).getSubReg()) {
|
||||
MachineOperand &MO = MI->getOperand(1);
|
||||
if (ImpDefRegs.count(MO.getReg())) {
|
||||
if (MO.isKill()) {
|
||||
LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg());
|
||||
vi.removeKill(MI);
|
||||
}
|
||||
MI->eraseFromParent();
|
||||
Changed = true;
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
bool ChangedToImpDef = false;
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand& MO = MI->getOperand(i);
|
||||
if (!MO.isReg() || !MO.isUse() || MO.isUndef())
|
||||
if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef())
|
||||
continue;
|
||||
unsigned Reg = MO.getReg();
|
||||
if (!Reg)
|
||||
@ -145,6 +159,12 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
|
||||
|
||||
Changed = true;
|
||||
MO.setIsUndef();
|
||||
// This is a partial register redef of an implicit def.
|
||||
// Make sure the whole register is defined by the instruction.
|
||||
if (MO.isDef()) {
|
||||
MI->addRegisterDefined(Reg);
|
||||
continue;
|
||||
}
|
||||
if (MO.isKill() || MI->isRegTiedToDefOperand(i)) {
|
||||
// Make sure other uses of
|
||||
for (unsigned j = i+1; j != e; ++j) {
|
||||
|
@ -1218,6 +1218,19 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
|
||||
DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
|
||||
}
|
||||
|
||||
// Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
|
||||
if (mi->isInsertSubreg()) {
|
||||
// From %reg = INSERT_SUBREG %reg, %subreg, subidx
|
||||
// To %reg:subidx = COPY %subreg
|
||||
unsigned SubIdx = mi->getOperand(3).getImm();
|
||||
mi->RemoveOperand(3);
|
||||
assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
|
||||
mi->getOperand(0).setSubReg(SubIdx);
|
||||
mi->RemoveOperand(1);
|
||||
mi->setDesc(TII->get(TargetOpcode::COPY));
|
||||
DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
|
||||
}
|
||||
|
||||
// Clear TiedOperands here instead of at the top of the loop
|
||||
// since most instructions do not have tied operands.
|
||||
TiedOperands.clear();
|
||||
|
Loading…
Reference in New Issue
Block a user