[Hexagon] Adding A2_sub instruction

Renaming test files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222263 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-11-18 21:51:51 +00:00
parent 063e54286c
commit ed37b1e2d0
3 changed files with 12 additions and 0 deletions

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@ -162,6 +162,7 @@ multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
let isCodeGenOnly = 0 in
defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
// Pats for instruction selection.
class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
@ -169,6 +170,7 @@ class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
(ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
def: BinOp32_pat<add, A2_add, i32>;
def: BinOp32_pat<sub, A2_sub, i32>;
multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {

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@ -0,0 +1,10 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -s - | FileCheck %s
define i32 @foo (i32 %a, i32 %b)
{
%1 = sub i32 %a, %b
ret i32 %1
}
; CHECK: 0000 004021f3 00c09f52