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[AMDGPU][MC] Fixed bugs in export instruction

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See Bugs 33019, 33056:
  https://bugs.llvm.org//show_bug.cgi?id=33019
  https://bugs.llvm.org//show_bug.cgi?id=33056

Reviewers: artem.tamazov, vpykhtin

Differential Revision: https://reviews.llvm.org/D33288

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303423 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dmitry Preobrazhensky 2017-05-19 13:36:09 +00:00
parent 95bb5cd8a2
commit ede5ffa4d3
4 changed files with 83 additions and 10 deletions
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25
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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@ -2796,6 +2796,7 @@ void AMDGPUAsmParser::cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
OptionalImmIndexMap OptionalIdx;
unsigned OperandIdx[4];
unsigned EnMask = 0;
int SrcIdx = 0;
@ -2804,15 +2805,18 @@ void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
// Add the register arguments
if (Op.isReg()) {
EnMask |= (1 << SrcIdx);
assert(SrcIdx < 4);
OperandIdx[SrcIdx] = Inst.size();
Op.addRegOperands(Inst, 1);
++SrcIdx;
continue;
}
if (Op.isOff()) {
++SrcIdx;
assert(SrcIdx < 4);
OperandIdx[SrcIdx] = Inst.size();
Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister));
++SrcIdx;
continue;
}
@ -2828,6 +2832,22 @@ void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
OptionalIdx[Op.getImmTy()] = i;
}
assert(SrcIdx == 4);
bool Compr = false;
if (OptionalIdx.find(AMDGPUOperand::ImmTyExpCompr) != OptionalIdx.end()) {
Compr = true;
Inst.getOperand(OperandIdx[1]) = Inst.getOperand(OperandIdx[2]);
Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister);
Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister);
}
for (auto i = 0; i < SrcIdx; ++i) {
if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) {
EnMask |= Compr? (0x3 << i * 2) : (0x1 << i);
}
}
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr);
@ -3642,6 +3662,7 @@ static const OptionalOperand AMDGPUOptionalOperandTable[] = {
{"src0_sel", AMDGPUOperand::ImmTySdwaSrc0Sel, false, nullptr},
{"src1_sel", AMDGPUOperand::ImmTySdwaSrc1Sel, false, nullptr},
{"dst_unused", AMDGPUOperand::ImmTySdwaDstUnused, false, nullptr},
{"compr", AMDGPUOperand::ImmTyExpCompr, true, nullptr },
{"vm", AMDGPUOperand::ImmTyExpVM, true, nullptr},
{"op_sel", AMDGPUOperand::ImmTyOpSel, false, nullptr},
{"op_sel_hi", AMDGPUOperand::ImmTyOpSelHi, false, nullptr},

16
lib/Target/AMDGPU/SIInstrFormats.td
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@ -228,10 +228,10 @@ class EXPe : Enc64 {
bits<1> compr;
bits<1> done;
bits<1> vm;
bits<8> vsrc0;
bits<8> vsrc1;
bits<8> vsrc2;
bits<8> vsrc3;
bits<8> src0;
bits<8> src1;
bits<8> src2;
bits<8> src3;
let Inst{3-0} = en;
let Inst{9-4} = tgt;
@ -239,10 +239,10 @@ class EXPe : Enc64 {
let Inst{11} = done;
let Inst{12} = vm;
let Inst{31-26} = 0x3e;
let Inst{39-32} = vsrc0;
let Inst{47-40} = vsrc1;
let Inst{55-48} = vsrc2;
let Inst{63-56} = vsrc3;
let Inst{39-32} = src0;
let Inst{47-40} = src1;
let Inst{55-48} = src2;
let Inst{63-56} = src3;
}
let Uses = [EXEC] in {

12
test/MC/AMDGPU/exp.s
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@ -112,3 +112,15 @@ exp mrt0 v4, v3, v2, v1 vm
exp mrt0 v4, v3, v2, v1 done vm
// SI: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xf8,0x04,0x03,0x02,0x01]
// VI: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xc4,0x04,0x03,0x02,0x01]
exp mrtz, v3, v3, v7, v7 compr
// SI: exp mrtz v3, v3, v7, v7 compr ; encoding: [0x8f,0x04,0x00,0xf8,0x03,0x07,0x00,0x00]
// VI: exp mrtz v3, v3, v7, v7 compr ; encoding: [0x8f,0x04,0x00,0xc4,0x03,0x07,0x00,0x00]
exp mrtz, off, off, v7, v7 compr
// SI: exp mrtz off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xf8,0x00,0x07,0x00,0x00]
// VI: exp mrtz off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xc4,0x00,0x07,0x00,0x00]
exp mrtz, v3, v3, off, off compr
// SI: exp mrtz v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xf8,0x03,0x00,0x00,0x00]
// VI: exp mrtz v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xc4,0x03,0x00,0x00,0x00]

40
test/MC/Disassembler/AMDGPU/exp_vi.txt Normal file
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@ -0,0 +1,40 @@
# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
# VI: exp mrt0 v1, v2, v3, v4 ; encoding: [0x0f,0x00,0x00,0xc4,0x01,0x02,0x03,0x04]
0x0f,0x00,0x00,0xc4,0x01,0x02,0x03,0x04
# VI: exp mrt0 v1, v2, v3, v4 vm ; encoding: [0x0f,0x10,0x00,0xc4,0x01,0x02,0x03,0x04]
0x0f,0x10,0x00,0xc4,0x01,0x02,0x03,0x04
# VI: exp mrt0 v1, v1, v3, v3 compr ; encoding: [0x0f,0x04,0x00,0xc4,0x01,0x03,0x00,0x00]
0x0f,0x04,0x00,0xc4,0x01,0x03,0x00,0x00
# VI: exp mrt0 v1, v2, v3, v4 done ; encoding: [0x0f,0x08,0x00,0xc4,0x01,0x02,0x03,0x04]
0x0f,0x08,0x00,0xc4,0x01,0x02,0x03,0x04
# VI: exp mrt0 v2, v2, v4, v4 done compr vm ; encoding: [0x0f,0x1c,0x00,0xc4,0x02,0x04,0x00,0x00]
0x0f,0x1c,0x00,0xc4,0x02,0x04,0x00,0x00
# VI: exp mrt0 v7, off, off, off vm ; encoding: [0x01,0x10,0x00,0xc4,0x07,0x00,0x00,0x00]
0x01,0x10,0x00,0xc4,0x07,0x00,0x00,0x00
# VI: exp mrt0 off, off, v1, v2 ; encoding: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x01,0x02]
0x0c,0x00,0x00,0xc4,0x00,0x00,0x01,0x02
# VI: exp mrt0 off, off, v8, v8 done compr ; encoding: [0x0c,0x0c,0x00,0xc4,0x00,0x08,0x00,0x00]
0x0c,0x0c,0x00,0xc4,0x00,0x08,0x00,0x00
# VI: exp mrt0 v1, v1, off, off compr ; encoding: [0x03,0x04,0x00,0xc4,0x01,0x00,0x00,0x00]
0x03,0x04,0x00,0xc4,0x01,0x00,0x00,0x00
# VI: exp param0 off, off, off, off compr ; encoding: [0x00,0x06,0x00,0xc4,0x00,0x00,0x00,0x00]
0x00,0x06,0x00,0xc4,0x00,0x00,0x00,0x00
# VI: exp mrtz v0, off, off, off done vm ; encoding: [0x81,0x18,0x00,0xc4,0x00,0x00,0x00,0x00]
0x81,0x18,0x00,0xc4,0x00,0x00,0x00,0x00
# VI: exp null v255, v0, v255, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0xff,0x00,0xff,0x00]
0x9f,0x00,0x00,0xc4,0xff,0x00,0xff,0x00
# VI: exp pos0 v1, off, off, off ; encoding: [0xc1,0x00,0x00,0xc4,0x01,0x00,0x00,0x00]
0xc1,0x00,0x00,0xc4,0x01,0x00,0x00,0x00