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Port a shift-by-1 optimization from LegalizeDAG: it

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was presumably added after the rest of the code was
copied to LegalizeTypes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53459 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands 2008-07-11 16:54:57 +00:00
parent dddc6291fb
commit edfba7e707
2 changed files with 12 additions and 0 deletions
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7
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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@ -1556,6 +1556,13 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
} else if (Amt == NVTBits) {
Lo = DAG.getConstant(0, NVT);
Hi = InL;
} else if (Amt == 1) {
// Emit this X << 1 as X+X.
SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
SDOperand LoOps[2] = { InL, InL };
Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
SDOperand HiOps[3] = { InH, InH, Lo.getValue(1) };
Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
} else {
Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
Hi = DAG.getNode(ISD::OR, NVT,

5
test/CodeGen/X86/2008-07-11-SHLBy1.ll Normal file
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@ -0,0 +1,5 @@
; RUN: llvm-as < %s | llc -march=x86-64 -o - | not grep shr
define i128 @sl(i128 %x) {
%t = shl i128 %x, 1
ret i128 %t
}