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ARM: address WoA division overflow crash
Disable custom handling of signed 32-bit and 64-bit integer divide. Add test cases for both 32-bit and 64-bit integer overflow crashes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253865 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Martell Malone
parent
4c91939703
commit
ee54187984
@ -395,6 +395,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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{ RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
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{ RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
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{ RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
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{ RTLIB::SDIV_I32, "__rt_sdiv", CallingConv::ARM_AAPCS_VFP },
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{ RTLIB::SDIV_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS_VFP },
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};
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for (const auto &LC : LibraryCalls) {
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@ -782,10 +784,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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}
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if (Subtarget->isTargetWindows() && !Subtarget->hasDivide()) {
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setOperationAction(ISD::SDIV, MVT::i32, Custom);
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setOperationAction(ISD::UDIV, MVT::i32, Custom);
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setOperationAction(ISD::SDIV, MVT::i64, Custom);
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setOperationAction(ISD::UDIV, MVT::i64, Custom);
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}
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@ -6667,7 +6667,6 @@ SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
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}
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SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,
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bool Signed,
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SDValue &Chain) const {
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EVT VT = Op.getValueType();
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assert((VT == MVT::i32 || VT == MVT::i64) &&
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@ -6678,10 +6677,7 @@ SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,
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const auto &TLI = DAG.getTargetLoweringInfo();
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const char *Name = nullptr;
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if (Signed)
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Name = (VT == MVT::i32) ? "__rt_sdiv" : "__rt_sdiv64";
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else
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Name = (VT == MVT::i32) ? "__rt_udiv" : "__rt_udiv64";
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Name = (VT == MVT::i32) ? "__rt_udiv" : "__rt_udiv64";
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SDValue ES = DAG.getExternalSymbol(Name, TLI.getPointerTy(DL));
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@ -6703,8 +6699,8 @@ SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,
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return LowerCallTo(CLI).first;
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}
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SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op, SelectionDAG &DAG,
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bool Signed) const {
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SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op,
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SelectionDAG &DAG) const {
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assert(Op.getValueType() == MVT::i32 &&
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"unexpected type for custom lowering DIV");
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SDLoc dl(Op);
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@ -6712,11 +6708,11 @@ SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op, SelectionDAG &DAG,
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SDValue DBZCHK = DAG.getNode(ARMISD::WIN__DBZCHK, dl, MVT::Other,
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DAG.getEntryNode(), Op.getOperand(1));
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return LowerWindowsDIVLibCall(Op, DAG, Signed, DBZCHK);
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return LowerWindowsDIVLibCall(Op, DAG, DBZCHK);
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}
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void ARMTargetLowering::ExpandDIV_Windows(
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SDValue Op, SelectionDAG &DAG, bool Signed,
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SDValue Op, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &Results) const {
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const auto &DL = DAG.getDataLayout();
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const auto &TLI = DAG.getTargetLoweringInfo();
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@ -6734,7 +6730,7 @@ void ARMTargetLowering::ExpandDIV_Windows(
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SDValue DBZCHK =
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DAG.getNode(ARMISD::WIN__DBZCHK, dl, MVT::Other, DAG.getEntryNode(), Or);
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SDValue Result = LowerWindowsDIVLibCall(Op, DAG, Signed, DBZCHK);
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SDValue Result = LowerWindowsDIVLibCall(Op, DAG, DBZCHK);
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SDValue Lower = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Result);
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SDValue Upper = DAG.getNode(ISD::SRL, dl, MVT::i64, Result,
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@ -6835,13 +6831,10 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
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case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
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case ISD::MUL: return LowerMUL(Op, DAG);
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case ISD::SDIV:
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if (Subtarget->isTargetWindows())
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return LowerDIV_Windows(Op, DAG, /* Signed */ true);
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return LowerSDIV(Op, DAG);
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case ISD::SDIV: return LowerSDIV(Op, DAG);
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case ISD::UDIV:
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if (Subtarget->isTargetWindows())
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return LowerDIV_Windows(Op, DAG, /* Signed */ false);
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return LowerDIV_Windows(Op, DAG);
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return LowerUDIV(Op, DAG);
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case ISD::ADDC:
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case ISD::ADDE:
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@ -6894,10 +6887,8 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
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ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
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return;
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case ISD::UDIV:
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case ISD::SDIV:
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assert(Subtarget->isTargetWindows() && "can only expand DIV on Windows");
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return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV,
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Results);
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return ExpandDIV_Windows(SDValue(N, 0), DAG, Results);
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}
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if (Res.getNode())
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Results.push_back(Res);
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@ -543,10 +543,10 @@ namespace llvm {
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const ARMSubtarget *ST) const;
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SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
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SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG) const;
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void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &Results) const;
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SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
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SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,
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SDValue &Chain) const;
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SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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@ -1,17 +1,6 @@
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; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s
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; RUN: llc -mtriple thumbv7-windows-msvc -filetype asm -o - %s | FileCheck %s
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define arm_aapcs_vfpcc i32 @sdiv32(i32 %divisor, i32 %divident) {
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entry:
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%div = sdiv i32 %divident, %divisor
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ret i32 %div
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}
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; CHECK-LABEL: sdiv32:
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; CHECK: cbz r0
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; CHECK: bl __rt_sdiv
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; CHECK: udf.w #249
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define arm_aapcs_vfpcc i32 @udiv32(i32 %divisor, i32 %divident) {
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entry:
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%div = udiv i32 %divident, %divisor
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@ -23,18 +12,6 @@ entry:
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; CHECK: bl __rt_udiv
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; CHECK: udf.w #249
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define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) {
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entry:
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%div = sdiv i64 %divident, %divisor
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ret i64 %div
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}
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; CHECK-LABEL: sdiv64:
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; CHECK: orr.w r12, r0, r1
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; CHECK-NEXT: cbz r12
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; CHECK: bl __rt_sdiv64
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; CHECK: udf.w #249
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define arm_aapcs_vfpcc i64 @udiv64(i64 %divisor, i64 %divident) {
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entry:
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%div = udiv i64 %divident, %divisor
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@ -1,6 +1,24 @@
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; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s
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; RUN: llc -mtriple thumbv7-windows-msvc -filetype asm -o - %s | FileCheck %s
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define arm_aapcs_vfpcc i32 @sdiv32(i32 %divisor, i32 %divident) {
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entry:
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%div = sdiv i32 %divident, %divisor
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ret i32 %div
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}
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; CHECK-LABEL: sdiv32
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; CHECK: b __rt_sdiv
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define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) {
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entry:
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%div = sdiv i64 %divident, %divisor
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ret i64 %div
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}
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; CHECK-LABEL: sdiv64
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; CHECK: bl __rt_sdiv64
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define arm_aapcs_vfpcc i64 @stoi64(float %f) {
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entry:
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%conv = fptosi float %f to i64
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39
test/CodeGen/ARM/Windows/overflow.ll
Normal file
39
test/CodeGen/ARM/Windows/overflow.ll
Normal file
@ -0,0 +1,39 @@
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; RUN: llc -mtriple thumbv7-windows-gnu -filetype asm -o - %s
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define i32 @divoverflow32(i32 %a, i32 %b) {
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = load i32, i32* %1, align 4
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%4 = load i32, i32* %2, align 4
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%5 = sub nsw i32 0, %4
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%6 = sdiv i32 -2147483647, %3
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%7 = icmp sgt i32 %5, %6
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br i1 %7, label %8, label %9
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call void (...) @abort_impl32()
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unreachable
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%10 = load i32, i32* %1, align 4
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%11 = load i32, i32* %2, align 4
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%12 = mul nsw i32 %10, %11
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ret i32 %12
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}
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declare void @abort_impl32(...)
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define i64 @divoverflow64(i64 %a, i64 %b) {
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%1 = alloca i64, align 8
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%2 = alloca i64, align 8
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%3 = load i64, i64* %1, align 8
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%4 = load i64, i64* %2, align 8
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%5 = sub nsw i64 0, %4
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%6 = sdiv i64 -9223372036854775808, %3
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%7 = icmp sgt i64 %5, %6
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br i1 %7, label %8, label %9
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call void (...) @abort_impl64()
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unreachable
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%10 = load i64, i64* %1, align 8
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%11 = load i64, i64* %2, align 8
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%12 = mul nsw i64 %10, %11
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ret i64 %12
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}
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declare void @abort_impl64(...)
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