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R600/SI: Use bcnt instruction for ctpop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210567 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
81ff9cdedb
commit
ee9772d9dd
@ -220,12 +220,19 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
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}
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for (MVT VT : { MVT::i32, MVT::i64 }) {
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// TODO: Evergreen has BCNT_INT for CTPOP
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setOperationAction(ISD::CTPOP, VT, Expand);
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setOperationAction(ISD::CTTZ, VT, Expand);
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setOperationAction(ISD::CTLZ, VT, Expand);
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}
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static const MVT::SimpleValueType IntTypes[] = {
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MVT::v2i32, MVT::v4i32
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};
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for (MVT VT : IntTypes) {
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//Expand the following operations for the current type by default
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// Expand the following operations for the current type by default.
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setOperationAction(ISD::ADD, VT, Expand);
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setOperationAction(ISD::AND, VT, Expand);
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setOperationAction(ISD::FP_TO_SINT, VT, Expand);
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@ -244,6 +251,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::VSELECT, VT, Expand);
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setOperationAction(ISD::XOR, VT, Expand);
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setOperationAction(ISD::BSWAP, VT, Expand);
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setOperationAction(ISD::CTPOP, VT, Expand);
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setOperationAction(ISD::CTTZ, VT, Expand);
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setOperationAction(ISD::CTLZ, VT, Expand);
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}
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static const MVT::SimpleValueType FloatTypes[] = {
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@ -125,11 +125,6 @@ void AMDGPUTargetLowering::InitAMDILLowering() {
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setOperationAction(ISD::UMUL_LOHI, VT, Expand);
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setOperationAction(ISD::BSWAP, VT, Expand);
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// GPU doesn't have any counting operators
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setOperationAction(ISD::CTPOP, VT, Expand);
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setOperationAction(ISD::CTTZ, VT, Expand);
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setOperationAction(ISD::CTLZ, VT, Expand);
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}
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for (MVT VT : VectorTypes) {
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@ -67,11 +67,8 @@ let TargetPrefix = "AMDIL", isTarget = 1 in {
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let TargetPrefix = "AMDIL", isTarget = 1 in {
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def int_AMDIL_abs : GCCBuiltin<"__amdil_abs">, UnaryIntInt;
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def int_AMDIL_bit_reverse_u32 : GCCBuiltin<"__amdil_ubit_reverse">,
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UnaryIntInt;
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def int_AMDIL_bit_count_i32 : GCCBuiltin<"__amdil_count_bits">,
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UnaryIntInt;
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def int_AMDIL_bit_find_first_lo : GCCBuiltin<"__amdil_ffb_lo">,
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UnaryIntInt;
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def int_AMDIL_bit_find_first_hi : GCCBuiltin<"__amdil_ffb_hi">,
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@ -211,6 +211,8 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FRINT, MVT::f64, Legal);
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}
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setOperationAction(ISD::CTPOP, MVT::i32, Legal);
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setTargetDAGCombine(ISD::SELECT_CC);
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setTargetDAGCombine(ISD::SETCC);
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@ -668,6 +668,7 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
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case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
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case AMDGPU::S_LOAD_DWORDX4_IMM:
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case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
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case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32;
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}
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}
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@ -1218,6 +1219,10 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
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// 3 to not hit an assertion later in MCInstLower.
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Inst->addOperand(MachineOperand::CreateImm(0));
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Inst->addOperand(MachineOperand::CreateImm(0));
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} else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
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// The VALU version adds the second operand to the result, so insert an
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// extra 0 operand.
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Inst->addOperand(MachineOperand::CreateImm(0));
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}
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addDescImplicitUseDef(NewDesc, Inst);
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@ -107,7 +107,9 @@ def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
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////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
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////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
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////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>;
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def S_BCNT1_I32_B32 : SOP1_32 <0x0000000f, "S_BCNT1_I32_B32",
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[(set i32:$dst, (ctpop i32:$src0))]
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>;
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////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>;
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////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>;
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////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
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@ -1217,7 +1219,7 @@ defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32",
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defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>;
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defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>;
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defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
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//defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
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defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
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defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
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defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
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@ -2508,6 +2510,11 @@ def : Pat <
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(S_ADD_I32 $src0, $src1)
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>;
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def : Pat <
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(i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
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(V_BCNT_U32_B32_e32 $popcnt, $val)
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>;
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//============================================================================//
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// Miscellaneous Optimization Patterns
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//============================================================================//
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203
test/CodeGen/R600/ctpop.ll
Normal file
203
test/CodeGen/R600/ctpop.ll
Normal file
@ -0,0 +1,203 @@
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare i32 @llvm.ctpop.i32(i32) nounwind readnone
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declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone
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declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
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declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>) nounwind readnone
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declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>) nounwind readnone
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; FUNC-LABEL: @s_ctpop_i32:
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; SI: S_LOAD_DWORD [[SVAL:s[0-9]+]],
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; SI: S_BCNT1_I32_B32 [[SRESULT:s[0-9]+]], [[SVAL]]
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; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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; SI: BUFFER_STORE_DWORD [[VRESULT]],
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; SI: S_ENDPGM
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define void @s_ctpop_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
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%ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
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store i32 %ctpop, i32 addrspace(1)* %out, align 4
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ret void
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}
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; XXX - Why 0 in register?
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; FUNC-LABEL: @v_ctpop_i32:
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; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]],
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; SI: V_MOV_B32_e32 [[VZERO:v[0-9]+]], 0
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; SI: V_BCNT_U32_B32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[VZERO]]
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; SI: BUFFER_STORE_DWORD [[RESULT]],
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; SI: S_ENDPGM
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define void @v_ctpop_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
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%val = load i32 addrspace(1)* %in, align 4
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%ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
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store i32 %ctpop, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_ctpop_add_chain_i32
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; SI: BUFFER_LOAD_DWORD [[VAL0:v[0-9]+]],
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; SI: BUFFER_LOAD_DWORD [[VAL1:v[0-9]+]],
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; SI: V_MOV_B32_e32 [[VZERO:v[0-9]+]], 0
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; SI: V_BCNT_U32_B32_e32 [[MIDRESULT:v[0-9]+]], [[VAL1]], [[VZERO]]
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; SI-NOT: ADD
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; SI: V_BCNT_U32_B32_e64 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
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; SI: BUFFER_STORE_DWORD [[RESULT]],
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; SI: S_ENDPGM
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define void @v_ctpop_add_chain_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in0, i32 addrspace(1)* noalias %in1) nounwind {
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%val0 = load i32 addrspace(1)* %in0, align 4
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%val1 = load i32 addrspace(1)* %in1, align 4
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%ctpop0 = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone
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%ctpop1 = call i32 @llvm.ctpop.i32(i32 %val1) nounwind readnone
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%add = add i32 %ctpop0, %ctpop1
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_ctpop_v2i32:
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: S_ENDPGM
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define void @v_ctpop_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %in) nounwind {
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%val = load <2 x i32> addrspace(1)* %in, align 8
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%ctpop = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %val) nounwind readnone
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store <2 x i32> %ctpop, <2 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @v_ctpop_v4i32:
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: S_ENDPGM
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define void @v_ctpop_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %in) nounwind {
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%val = load <4 x i32> addrspace(1)* %in, align 16
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%ctpop = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %val) nounwind readnone
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store <4 x i32> %ctpop, <4 x i32> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: @v_ctpop_v8i32:
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: S_ENDPGM
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define void @v_ctpop_v8i32(<8 x i32> addrspace(1)* noalias %out, <8 x i32> addrspace(1)* noalias %in) nounwind {
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%val = load <8 x i32> addrspace(1)* %in, align 32
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%ctpop = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %val) nounwind readnone
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store <8 x i32> %ctpop, <8 x i32> addrspace(1)* %out, align 32
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ret void
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}
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; FUNC-LABEL: @v_ctpop_v16i32:
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: V_BCNT_U32_B32_e32
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; SI: S_ENDPGM
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define void @v_ctpop_v16i32(<16 x i32> addrspace(1)* noalias %out, <16 x i32> addrspace(1)* noalias %in) nounwind {
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%val = load <16 x i32> addrspace(1)* %in, align 32
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%ctpop = call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %val) nounwind readnone
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store <16 x i32> %ctpop, <16 x i32> addrspace(1)* %out, align 32
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ret void
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}
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; FUNC-LABEL: @v_ctpop_i32_add_inline_constant:
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; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]],
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; SI: V_BCNT_U32_B32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
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; SI: BUFFER_STORE_DWORD [[RESULT]],
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; SI: S_ENDPGM
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define void @v_ctpop_i32_add_inline_constant(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
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%val = load i32 addrspace(1)* %in, align 4
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%ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
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%add = add i32 %ctpop, 4
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_ctpop_i32_add_inline_constant_inv:
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; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]],
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; SI: V_BCNT_U32_B32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
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; SI: BUFFER_STORE_DWORD [[RESULT]],
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; SI: S_ENDPGM
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define void @v_ctpop_i32_add_inline_constant_inv(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
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%val = load i32 addrspace(1)* %in, align 4
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%ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
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%add = add i32 4, %ctpop
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_ctpop_i32_add_literal:
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; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]],
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; SI: V_MOV_B32_e32 [[LIT:v[0-9]+]], 0x1869f
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; SI: V_BCNT_U32_B32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[LIT]]
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; SI: BUFFER_STORE_DWORD [[RESULT]],
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; SI: S_ENDPGM
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define void @v_ctpop_i32_add_literal(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
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%val = load i32 addrspace(1)* %in, align 4
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%ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
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%add = add i32 %ctpop, 99999
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_ctpop_i32_add_var:
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; SI-DAG: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]],
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; SI-DAG: S_LOAD_DWORD [[VAR:s[0-9]+]],
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; SI: V_BCNT_U32_B32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]]
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; SI: BUFFER_STORE_DWORD [[RESULT]],
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; SI: S_ENDPGM
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define void @v_ctpop_i32_add_var(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %const) nounwind {
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%val = load i32 addrspace(1)* %in, align 4
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%ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
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%add = add i32 %ctpop, %const
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_ctpop_i32_add_var_inv:
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; SI-DAG: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]],
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; SI-DAG: S_LOAD_DWORD [[VAR:s[0-9]+]],
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; SI: V_BCNT_U32_B32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]]
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; SI: BUFFER_STORE_DWORD [[RESULT]],
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; SI: S_ENDPGM
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define void @v_ctpop_i32_add_var_inv(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %const) nounwind {
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%val = load i32 addrspace(1)* %in, align 4
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%ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
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%add = add i32 %const, %ctpop
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_ctpop_i32_add_vvar_inv
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; SI-DAG: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], {{.*}} + 0x0
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; SI-DAG: BUFFER_LOAD_DWORD [[VAR:v[0-9]+]], {{.*}} + 0x10
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; SI: V_BCNT_U32_B32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]]
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; SI: BUFFER_STORE_DWORD [[RESULT]],
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; SI: S_ENDPGM
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define void @v_ctpop_i32_add_vvar_inv(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 addrspace(1)* noalias %constptr) nounwind {
|
||||
%val = load i32 addrspace(1)* %in, align 4
|
||||
%ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
|
||||
%gep = getelementptr i32 addrspace(1)* %constptr, i32 4
|
||||
%const = load i32 addrspace(1)* %gep, align 4
|
||||
%add = add i32 %const, %ctpop
|
||||
store i32 %add, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
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Reference in New Issue
Block a user