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ARM NEON relax parse time diagnostics for alignment specifiers.

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There's more variation that we need to handle. Error checking will need
to be on operand predicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-12-19 18:31:43 +00:00
parent 3346dcef02
commit eeaf1c1636
4 changed files with 19 additions and 17 deletions
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5
lib/Target/ARM/ARMInstrNEON.td
View File

@ -819,12 +819,11 @@ def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
}
def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
let Inst{7-6} = lane{1-0};
let Inst{4} = Rn{4};
let Inst{5-4} = Rn{5-4};
}
def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
let Inst{7} = lane{0};
let Inst{5} = Rn{4};
let Inst{4} = Rn{4};
let Inst{5-4} = Rn{5-4};
}
def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;

7
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -361,7 +361,7 @@ class ARMOperand : public MCParsedAsmOperand {
ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
unsigned ShiftImm; // shift for OffsetReg.
unsigned Alignment; // 0 = no alignment specified
// n = alignment in bytes (8, 16, or 32)
// n = alignment in bytes (2, 4, 8, 16, or 32)
unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
} Memory;
@ -3954,7 +3954,10 @@ parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
unsigned Align = 0;
switch (CE->getValue()) {
default:
return Error(E, "alignment specifier must be 64, 128, or 256 bits");
return Error(E,
"alignment specifier must be 16, 32, 64, 128, or 256 bits");
case 16: Align = 2; break;
case 32: Align = 4; break;
case 64: Align = 8; break;
case 128: Align = 16; break;
case 256: Align = 32; break;

8
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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@ -1372,11 +1372,11 @@ getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
switch (Imm.getImm()) {
default: break;
case 2:
case 4:
case 8:
case 16: Align = 0x00; break;
case 32: Align = 0x03; break;
case 16:
case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
case 2: Align = 0x00; break;
case 4: Align = 0x03; break;
}
return RegNo | (Align << 4);

16
test/MC/ARM/neon-vld-encoding.s
View File

@ -211,24 +211,24 @@
@ CHECK: vld1.8 {d4[], d5[]}, [r1], r3 @ encoding: [0x23,0x4c,0xa1,0xf4]
vld1.8 {d16[3]}, [r0]
@ vld1.16 {d16[2]}, [r0, :16]
@ vld1.32 {d16[1]}, [r0, :32]
vld1.16 {d16[2]}, [r0, :16]
vld1.32 {d16[1]}, [r0, :32]
vld1.p8 d12[6], [r2]!
vld1.i8 d12[6], [r2], r2
vld1.u16 d12[3], [r2]!
vld1.16 d12[2], [r2], r2
@ CHECK: vld1.8 {d16[3]}, [r0] @ encoding: [0x6f,0x00,0xe0,0xf4]
@ FIXME: vld1.16 {d16[2]}, [r0, :16] @ encoding: [0x9f,0x04,0xe0,0xf4]
@ FIXME: vld1.32 {d16[1]}, [r0, :32] @ encoding: [0xbf,0x08,0xe0,0xf4]
@ CHECK: vld1.16 {d16[2]}, [r0, :16] @ encoding: [0x9f,0x04,0xe0,0xf4]
@ CHECK: vld1.32 {d16[1]}, [r0, :32] @ encoding: [0xbf,0x08,0xe0,0xf4]
@ CHECK: vld1.8 {d12[6]}, [r2]! @ encoding: [0xcd,0xc0,0xa2,0xf4]
@ CHECK: vld1.8 {d12[6]}, [r2], r2 @ encoding: [0xc2,0xc0,0xa2,0xf4]
@ CHECK: vld1.16 {d12[3]}, [r2]! @ encoding: [0xcd,0xc4,0xa2,0xf4]
@ CHECK: vld1.16 {d12[2]}, [r2], r2 @ encoding: [0x82,0xc4,0xa2,0xf4]
@ vld2.8 {d16[1], d17[1]}, [r0, :16]
@ vld2.16 {d16[1], d17[1]}, [r0, :32]
vld2.8 {d16[1], d17[1]}, [r0, :16]
vld2.16 {d16[1], d17[1]}, [r0, :32]
vld2.32 {d16[1], d17[1]}, [r0]
@ vld2.16 {d17[1], d19[1]}, [r0]
@ vld2.32 {d17[0], d19[0]}, [r0, :64]
@ -236,8 +236,8 @@
vld2.8 {d2[4], d3[4]}, [r2]!
vld2.8 {d2[4], d3[4]}, [r2]
@ FIXME: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4]
@ FIXME: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4]
@ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4]
@ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4]
@ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf4]
@ FIXME: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4]
@ FIXME: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4]