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Change SelectCode's argument from SDValue to SDNode *, to make it more

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clear what information these functions are actually using.

This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92564 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2010-01-05 01:24:18 +00:00
parent 4c3235595f
commit eeb3a00b84
18 changed files with 562 additions and 552 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/CodeGen/DAGISelHeader.h
View File

@ -109,7 +109,7 @@ void SelectRoot(SelectionDAG &DAG) {
#if 0
DAG.setSubgraphColor(Node, "red");
#endif
SDNode *ResNode = Select(SDValue(Node, 0));
SDNode *ResNode = Select(Node);
// If node should not be replaced, continue with the next one.
if (ResNode == Node)
continue;

10
include/llvm/CodeGen/SelectionDAGISel.h
View File

@ -111,11 +111,11 @@ protected:
int64_t DesiredMaskS) const;
// Calls to these functions are generated by tblgen.
SDNode *Select_INLINEASM(SDValue N);
SDNode *Select_UNDEF(const SDValue &N);
SDNode *Select_EH_LABEL(const SDValue &N);
void CannotYetSelect(SDValue N);
void CannotYetSelectIntrinsic(SDValue N);
SDNode *Select_INLINEASM(SDNode *N);
SDNode *Select_UNDEF(SDNode *N);
SDNode *Select_EH_LABEL(SDNode *N);
void CannotYetSelect(SDNode *N);
void CannotYetSelectIntrinsic(SDNode *N);
private:
void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,

26
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1302,43 +1302,43 @@ bool SelectionDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
return !isNonImmUse(Root, N, U);
}
SDNode *SelectionDAGISel::Select_INLINEASM(SDValue N) {
std::vector<SDValue> Ops(N.getNode()->op_begin(), N.getNode()->op_end());
SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
std::vector<SDValue> Ops(N->op_begin(), N->op_end());
SelectInlineAsmMemoryOperands(Ops);
std::vector<EVT> VTs;
VTs.push_back(MVT::Other);
VTs.push_back(MVT::Flag);
SDValue New = CurDAG->getNode(ISD::INLINEASM, N.getDebugLoc(),
SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
VTs, &Ops[0], Ops.size());
return New.getNode();
}
SDNode *SelectionDAGISel::Select_UNDEF(const SDValue &N) {
return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::IMPLICIT_DEF,
N.getValueType());
SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
return CurDAG->SelectNodeTo(N, TargetInstrInfo::IMPLICIT_DEF,
N->getValueType(0));
}
SDNode *SelectionDAGISel::Select_EH_LABEL(const SDValue &N) {
SDValue Chain = N.getOperand(0);
SDNode *SelectionDAGISel::Select_EH_LABEL(SDNode *N) {
SDValue Chain = N->getOperand(0);
unsigned C = cast<LabelSDNode>(N)->getLabelID();
SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);
return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::EH_LABEL,
return CurDAG->SelectNodeTo(N, TargetInstrInfo::EH_LABEL,
MVT::Other, Tmp, Chain);
}
void SelectionDAGISel::CannotYetSelect(SDValue N) {
void SelectionDAGISel::CannotYetSelect(SDNode *N) {
std::string msg;
raw_string_ostream Msg(msg);
Msg << "Cannot yet select: ";
N.getNode()->print(Msg, CurDAG);
N->print(Msg, CurDAG);
llvm_report_error(Msg.str());
}
void SelectionDAGISel::CannotYetSelectIntrinsic(SDValue N) {
void SelectionDAGISel::CannotYetSelectIntrinsic(SDNode *N) {
errs() << "Cannot yet select: ";
unsigned iid =
cast<ConstantSDNode>(N.getOperand(N.getOperand(0).getValueType() == MVT::Other))->getZExtValue();
cast<ConstantSDNode>(N->getOperand(N->getOperand(0).getValueType() == MVT::Other))->getZExtValue();
if (iid < Intrinsic::num_intrinsics)
llvm_report_error("Cannot yet select: intrinsic %" + Intrinsic::getName((Intrinsic::ID)iid));
else if (const TargetIntrinsicInfo *tii = TM.getIntrinsicInfo())

321
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -64,53 +64,53 @@ public:
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
SDNode *Select(SDValue Op);
SDNode *Select(SDNode *N);
virtual void InstructionSelect();
bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
bool SelectShifterOperandReg(SDNode *Op, SDValue N, SDValue &A,
SDValue &B, SDValue &C);
bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
bool SelectAddrMode2(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Offset, SDValue &Opc);
bool SelectAddrMode2Offset(SDValue Op, SDValue N,
bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
SDValue &Offset, SDValue &Opc);
bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
bool SelectAddrMode3(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Offset, SDValue &Opc);
bool SelectAddrMode3Offset(SDValue Op, SDValue N,
bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
SDValue &Offset, SDValue &Opc);
bool SelectAddrMode4(SDValue Op, SDValue N, SDValue &Addr,
bool SelectAddrMode4(SDNode *Op, SDValue N, SDValue &Addr,
SDValue &Mode);
bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
bool SelectAddrMode5(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Offset);
bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
bool SelectAddrMode6(SDNode *Op, SDValue N, SDValue &Addr, SDValue &Update,
SDValue &Opc, SDValue &Align);
bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
bool SelectAddrModePC(SDNode *Op, SDValue N, SDValue &Offset,
SDValue &Label);
bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
bool SelectThumbAddrModeRR(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Offset);
bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
bool SelectThumbAddrModeRI5(SDNode *Op, SDValue N, unsigned Scale,
SDValue &Base, SDValue &OffImm,
SDValue &Offset);
bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
bool SelectThumbAddrModeS1(SDNode *Op, SDValue N, SDValue &Base,
SDValue &OffImm, SDValue &Offset);
bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
bool SelectThumbAddrModeS2(SDNode *Op, SDValue N, SDValue &Base,
SDValue &OffImm, SDValue &Offset);
bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
bool SelectThumbAddrModeS4(SDNode *Op, SDValue N, SDValue &Base,
SDValue &OffImm, SDValue &Offset);
bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
bool SelectThumbAddrModeSP(SDNode *Op, SDValue N, SDValue &Base,
SDValue &OffImm);
bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
bool SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
SDValue &BaseReg, SDValue &Opc);
bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
bool SelectT2AddrModeImm12(SDNode *Op, SDValue N, SDValue &Base,
SDValue &OffImm);
bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
bool SelectT2AddrModeImm8(SDNode *Op, SDValue N, SDValue &Base,
SDValue &OffImm);
bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
SDValue &OffImm);
bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
bool SelectT2AddrModeImm8s4(SDNode *Op, SDValue N, SDValue &Base,
SDValue &OffImm);
bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
bool SelectT2AddrModeSoReg(SDNode *Op, SDValue N, SDValue &Base,
SDValue &OffReg, SDValue &ShImm);
// Include the pieces autogenerated from the target description.
@ -119,48 +119,48 @@ public:
private:
/// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
/// ARM.
SDNode *SelectARMIndexedLoad(SDValue Op);
SDNode *SelectT2IndexedLoad(SDValue Op);
SDNode *SelectARMIndexedLoad(SDNode *N);
SDNode *SelectT2IndexedLoad(SDNode *N);
/// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
SDNode *SelectDYN_ALLOC(SDValue Op);
SDNode *SelectDYN_ALLOC(SDNode *N);
/// SelectVLD - Select NEON load intrinsics. NumVecs should
/// be 2, 3 or 4. The opcode arrays specify the instructions used for
/// loads of D registers and even subregs and odd subregs of Q registers.
/// For NumVecs == 2, QOpcodes1 is not used.
SDNode *SelectVLD(SDValue Op, unsigned NumVecs, unsigned *DOpcodes,
SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
unsigned *QOpcodes0, unsigned *QOpcodes1);
/// SelectVST - Select NEON store intrinsics. NumVecs should
/// be 2, 3 or 4. The opcode arrays specify the instructions used for
/// stores of D registers and even subregs and odd subregs of Q registers.
/// For NumVecs == 2, QOpcodes1 is not used.
SDNode *SelectVST(SDValue Op, unsigned NumVecs, unsigned *DOpcodes,
SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
unsigned *QOpcodes0, unsigned *QOpcodes1);
/// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
/// be 2, 3 or 4. The opcode arrays specify the instructions used for
/// load/store of D registers and even subregs and odd subregs of Q registers.
SDNode *SelectVLDSTLane(SDValue Op, bool IsLoad, unsigned NumVecs,
SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
unsigned *DOpcodes, unsigned *QOpcodes0,
unsigned *QOpcodes1);
/// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
SDNode *SelectV6T2BitfieldExtractOp(SDValue Op, unsigned Opc);
SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, unsigned Opc);
/// SelectCMOVOp - Select CMOV instructions for ARM.
SDNode *SelectCMOVOp(SDValue Op);
SDNode *SelectT2CMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
SDNode *SelectCMOVOp(SDNode *N);
SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
ARMCC::CondCodes CCVal, SDValue CCR,
SDValue InFlag);
SDNode *SelectARMCMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
ARMCC::CondCodes CCVal, SDValue CCR,
SDValue InFlag);
SDNode *SelectT2CMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
SDNode *SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
ARMCC::CondCodes CCVal, SDValue CCR,
SDValue InFlag);
SDNode *SelectARMCMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
ARMCC::CondCodes CCVal, SDValue CCR,
SDValue InFlag);
@ -206,7 +206,7 @@ void ARMDAGToDAGISel::InstructionSelect() {
CurDAG->RemoveDeadNodes();
}
bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
bool ARMDAGToDAGISel::SelectShifterOperandReg(SDNode *Op,
SDValue N,
SDValue &BaseReg,
SDValue &ShReg,
@ -230,7 +230,7 @@ bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
return true;
}
bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectAddrMode2(SDNode *Op, SDValue N,
SDValue &Base, SDValue &Offset,
SDValue &Opc) {
if (N.getOpcode() == ISD::MUL) {
@ -340,9 +340,9 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
return true;
}
bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
SDValue &Offset, SDValue &Opc) {
unsigned Opcode = Op.getOpcode();
unsigned Opcode = Op->getOpcode();
ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
? cast<LoadSDNode>(Op)->getAddressingMode()
: cast<StoreSDNode>(Op)->getAddressingMode();
@ -379,7 +379,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
}
bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectAddrMode3(SDNode *Op, SDValue N,
SDValue &Base, SDValue &Offset,
SDValue &Opc) {
if (N.getOpcode() == ISD::SUB) {
@ -429,9 +429,9 @@ bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
return true;
}
bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
SDValue &Offset, SDValue &Opc) {
unsigned Opcode = Op.getOpcode();
unsigned Opcode = Op->getOpcode();
ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
? cast<LoadSDNode>(Op)->getAddressingMode()
: cast<StoreSDNode>(Op)->getAddressingMode();
@ -451,14 +451,14 @@ bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
return true;
}
bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectAddrMode4(SDNode *Op, SDValue N,
SDValue &Addr, SDValue &Mode) {
Addr = N;
Mode = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectAddrMode5(SDNode *Op, SDValue N,
SDValue &Base, SDValue &Offset) {
if (N.getOpcode() != ISD::ADD) {
Base = N;
@ -506,7 +506,7 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
return true;
}
bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Op, SDValue N,
SDValue &Addr, SDValue &Update,
SDValue &Opc, SDValue &Align) {
Addr = N;
@ -518,7 +518,7 @@ bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
return true;
}
bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectAddrModePC(SDNode *Op, SDValue N,
SDValue &Offset, SDValue &Label) {
if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
Offset = N.getOperand(0);
@ -530,10 +530,10 @@ bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
return false;
}
bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N,
SDValue &Base, SDValue &Offset){
// FIXME dl should come from the parent load or store, not the address
DebugLoc dl = Op.getDebugLoc();
DebugLoc dl = Op->getDebugLoc();
if (N.getOpcode() != ISD::ADD) {
ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
if (!NC || NC->getZExtValue() != 0)
@ -549,7 +549,7 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
}
bool
ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDNode *Op, SDValue N,
unsigned Scale, SDValue &Base,
SDValue &OffImm, SDValue &Offset) {
if (Scale == 4) {
@ -605,25 +605,25 @@ ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
return true;
}
bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDNode *Op, SDValue N,
SDValue &Base, SDValue &OffImm,
SDValue &Offset) {
return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
}
bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDNode *Op, SDValue N,
SDValue &Base, SDValue &OffImm,
SDValue &Offset) {
return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
}
bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDNode *Op, SDValue N,
SDValue &Base, SDValue &OffImm,
SDValue &Offset) {
return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
}
bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDNode *Op, SDValue N,
SDValue &Base, SDValue &OffImm) {
if (N.getOpcode() == ISD::FrameIndex) {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
@ -659,7 +659,7 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
return false;
}
bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
SDValue &BaseReg,
SDValue &Opc) {
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
@ -679,7 +679,7 @@ bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
return false;
}
bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDNode *Op, SDValue N,
SDValue &Base, SDValue &OffImm) {
// Match simple R + imm12 operands.
@ -729,7 +729,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
return true;
}
bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDNode *Op, SDValue N,
SDValue &Base, SDValue &OffImm) {
// Match simple R - imm8 operands.
if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
@ -753,9 +753,9 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
return false;
}
bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
SDValue &OffImm){
unsigned Opcode = Op.getOpcode();
unsigned Opcode = Op->getOpcode();
ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
? cast<LoadSDNode>(Op)->getAddressingMode()
: cast<StoreSDNode>(Op)->getAddressingMode();
@ -772,7 +772,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
return false;
}
bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDNode *Op, SDValue N,
SDValue &Base, SDValue &OffImm) {
if (N.getOpcode() == ISD::ADD) {
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
@ -798,7 +798,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
return false;
}
bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDNode *Op, SDValue N,
SDValue &Base,
SDValue &OffReg, SDValue &ShImm) {
// (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
@ -854,8 +854,8 @@ static inline SDValue getAL(SelectionDAG *CurDAG) {
return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
}
SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
LoadSDNode *LD = cast<LoadSDNode>(Op);
SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
LoadSDNode *LD = cast<LoadSDNode>(N);
ISD::MemIndexedMode AM = LD->getAddressingMode();
if (AM == ISD::UNINDEXED)
return NULL;
@ -866,23 +866,23 @@ SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
unsigned Opcode = 0;
bool Match = false;
if (LoadedVT == MVT::i32 &&
SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
Match = true;
} else if (LoadedVT == MVT::i16 &&
SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
Match = true;
Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
: (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
} else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
if (LD->getExtensionType() == ISD::SEXTLOAD) {
if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
Match = true;
Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
}
} else {
if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
Match = true;
Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
}
@ -894,15 +894,15 @@ SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), Chain };
return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
MVT::Other, Ops, 6);
}
return NULL;
}
SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
LoadSDNode *LD = cast<LoadSDNode>(Op);
SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
LoadSDNode *LD = cast<LoadSDNode>(N);
ISD::MemIndexedMode AM = LD->getAddressingMode();
if (AM == ISD::UNINDEXED)
return NULL;
@ -913,7 +913,7 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
unsigned Opcode = 0;
bool Match = false;
if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
switch (LoadedVT.getSimpleVT().SimpleTy) {
case MVT::i32:
Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
@ -942,20 +942,19 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), Chain };
return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
MVT::Other, Ops, 5);
}
return NULL;
}
SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
SDNode *N = Op.getNode();
SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
EVT VT = Op.getValueType();
SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1);
SDValue Align = Op.getOperand(2);
EVT VT = N->getValueType(0);
SDValue Chain = N->getOperand(0);
SDValue Size = N->getOperand(1);
SDValue Align = N->getOperand(2);
SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
if (AlignVal < 0)
@ -1030,15 +1029,14 @@ static EVT GetNEONSubregVT(EVT VT) {
}
}
SDNode *ARMDAGToDAGISel::SelectVLD(SDValue Op, unsigned NumVecs,
SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
unsigned *DOpcodes, unsigned *QOpcodes0,
unsigned *QOpcodes1) {
assert(NumVecs >=2 && NumVecs <= 4 && "VLD NumVecs out-of-range");
SDNode *N = Op.getNode();
DebugLoc dl = N->getDebugLoc();
SDValue MemAddr, MemUpdate, MemOpc, Align;
if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
return NULL;
SDValue Chain = N->getOperand(0);
@ -1124,15 +1122,14 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDValue Op, unsigned NumVecs,
return NULL;
}
SDNode *ARMDAGToDAGISel::SelectVST(SDValue Op, unsigned NumVecs,
SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
unsigned *DOpcodes, unsigned *QOpcodes0,
unsigned *QOpcodes1) {
assert(NumVecs >=2 && NumVecs <= 4 && "VST NumVecs out-of-range");
SDNode *N = Op.getNode();
DebugLoc dl = N->getDebugLoc();
SDValue MemAddr, MemUpdate, MemOpc, Align;
if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
return NULL;
SDValue Chain = N->getOperand(0);
@ -1225,16 +1222,15 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDValue Op, unsigned NumVecs,
return NULL;
}
SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDValue Op, bool IsLoad,
SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
unsigned NumVecs, unsigned *DOpcodes,
unsigned *QOpcodes0,
unsigned *QOpcodes1) {
assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
SDNode *N = Op.getNode();
DebugLoc dl = N->getDebugLoc();
SDValue MemAddr, MemUpdate, MemOpc, Align;
if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
return NULL;
SDValue Chain = N->getOperand(0);
@ -1324,38 +1320,38 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDValue Op, bool IsLoad,
return NULL;
}
SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDValue Op,
SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
unsigned Opc) {
if (!Subtarget->hasV6T2Ops())
return NULL;
unsigned Shl_imm = 0;
if (isOpcWithIntImmediate(Op.getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
unsigned Srl_imm = 0;
if (isInt32Immediate(Op.getOperand(1), Srl_imm)) {
if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
unsigned Width = 32 - Srl_imm;
int LSB = Srl_imm - Shl_imm;
if (LSB < 0)
return NULL;
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { Op.getOperand(0).getOperand(0),
SDValue Ops[] = { N->getOperand(0).getOperand(0),
CurDAG->getTargetConstant(LSB, MVT::i32),
CurDAG->getTargetConstant(Width, MVT::i32),
getAL(CurDAG), Reg0 };
return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32, Ops, 5);
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
}
}
return NULL;
}
SDNode *ARMDAGToDAGISel::
SelectT2CMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
SDValue CPTmp0;
SDValue CPTmp1;
if (SelectT2ShifterOperandReg(Op, TrueVal, CPTmp0, CPTmp1)) {
if (SelectT2ShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1)) {
unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
unsigned Opc = 0;
@ -1372,27 +1368,27 @@ SelectT2CMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
}
return 0;
}
SDNode *ARMDAGToDAGISel::
SelectARMCMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
SDValue CPTmp0;
SDValue CPTmp1;
SDValue CPTmp2;
if (SelectShifterOperandReg(Op, TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
if (SelectShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
}
return 0;
}
SDNode *ARMDAGToDAGISel::
SelectT2CMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
if (!T)
@ -1402,14 +1398,14 @@ SelectT2CMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(),
return CurDAG->SelectNodeTo(N,
ARM::t2MOVCCi, MVT::i32, Ops, 5);
}
return 0;
}
SDNode *ARMDAGToDAGISel::
SelectARMCMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
if (!T)
@ -1419,19 +1415,19 @@ SelectARMCMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(),
return CurDAG->SelectNodeTo(N,
ARM::MOVCCi, MVT::i32, Ops, 5);
}
return 0;
}
SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDValue Op) {
EVT VT = Op.getValueType();
SDValue FalseVal = Op.getOperand(0);
SDValue TrueVal = Op.getOperand(1);
SDValue CC = Op.getOperand(2);
SDValue CCR = Op.getOperand(3);
SDValue InFlag = Op.getOperand(4);
SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
EVT VT = N->getValueType(0);
SDValue FalseVal = N->getOperand(0);
SDValue TrueVal = N->getOperand(1);
SDValue CC = N->getOperand(2);
SDValue CCR = N->getOperand(3);
SDValue InFlag = N->getOperand(4);
assert(CC.getOpcode() == ISD::Constant);
assert(CCR.getOpcode() == ISD::Register);
ARMCC::CondCodes CCVal =
@ -1445,18 +1441,18 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDValue Op) {
SDValue CPTmp1;
SDValue CPTmp2;
if (Subtarget->isThumb()) {
SDNode *Res = SelectT2CMOVShiftOp(Op, FalseVal, TrueVal,
SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
CCVal, CCR, InFlag);
if (!Res)
Res = SelectT2CMOVShiftOp(Op, TrueVal, FalseVal,
Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
if (Res)
return Res;
} else {
SDNode *Res = SelectARMCMOVShiftOp(Op, FalseVal, TrueVal,
SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
CCVal, CCR, InFlag);
if (!Res)
Res = SelectARMCMOVShiftOp(Op, TrueVal, FalseVal,
Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
if (Res)
return Res;
@ -1469,18 +1465,18 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDValue Op) {
// (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
// Pattern complexity = 10 cost = 1 size = 0
if (Subtarget->isThumb()) {
SDNode *Res = SelectT2CMOVSoImmOp(Op, FalseVal, TrueVal,
SDNode *Res = SelectT2CMOVSoImmOp(N, FalseVal, TrueVal,
CCVal, CCR, InFlag);
if (!Res)
Res = SelectT2CMOVSoImmOp(Op, TrueVal, FalseVal,
Res = SelectT2CMOVSoImmOp(N, TrueVal, FalseVal,
ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
if (Res)
return Res;
} else {
SDNode *Res = SelectARMCMOVSoImmOp(Op, FalseVal, TrueVal,
SDNode *Res = SelectARMCMOVSoImmOp(N, FalseVal, TrueVal,
CCVal, CCR, InFlag);
if (!Res)
Res = SelectARMCMOVSoImmOp(Op, TrueVal, FalseVal,
Res = SelectARMCMOVSoImmOp(N, TrueVal, FalseVal,
ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
if (Res)
return Res;
@ -1514,11 +1510,10 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDValue Op) {
Opc = ARM::VMOVDcc;
break;
}
return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
}
SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.getNode();
SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
if (N->isMachineOpcode())
@ -1569,7 +1564,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
Ops, 6);
}
ReplaceUses(Op, SDValue(ResNode, 0));
ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
return NULL;
}
@ -1593,28 +1588,28 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
}
}
case ARMISD::DYN_ALLOC:
return SelectDYN_ALLOC(Op);
return SelectDYN_ALLOC(N);
case ISD::SRL:
if (SDNode *I = SelectV6T2BitfieldExtractOp(Op,
if (SDNode *I = SelectV6T2BitfieldExtractOp(N,
Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX))
return I;
break;
case ISD::SRA:
if (SDNode *I = SelectV6T2BitfieldExtractOp(Op,
if (SDNode *I = SelectV6T2BitfieldExtractOp(N,
Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX))
return I;
break;
case ISD::MUL:
if (Subtarget->isThumb1Only())
break;
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
unsigned RHSV = C->getZExtValue();
if (!RHSV) break;
if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
unsigned ShImm = Log2_32(RHSV-1);
if (ShImm >= 32)
break;
SDValue V = Op.getOperand(0);
SDValue V = N->getOperand(0);
ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
@ -1630,7 +1625,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
unsigned ShImm = Log2_32(RHSV+1);
if (ShImm >= 32)
break;
SDValue V = Op.getOperand(0);
SDValue V = N->getOperand(0);
ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
@ -1650,7 +1645,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
// are entirely contributed by c2 and lower 16-bits are entirely contributed
// by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
// Select it to: "movt x, ((c1 & 0xffff) >> 16)
EVT VT = Op.getValueType();
EVT VT = N->getValueType(0);
if (VT != MVT::i32)
break;
unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
@ -1658,7 +1653,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
: (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
if (!Opc)
break;
SDValue N0 = Op.getOperand(0), N1 = Op.getOperand(1);
SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
if (!N1C)
break;
@ -1683,18 +1678,18 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
}
case ARMISD::VMOVRRD:
return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
Op.getOperand(0), getAL(CurDAG),
N->getOperand(0), getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32));
case ISD::UMUL_LOHI: {
if (Subtarget->isThumb1Only())
break;
if (Subtarget->isThumb()) {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
} else {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
@ -1704,11 +1699,11 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
if (Subtarget->isThumb1Only())
break;
if (Subtarget->isThumb()) {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
} else {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
@ -1717,9 +1712,9 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
case ISD::LOAD: {
SDNode *ResNode = 0;
if (Subtarget->isThumb() && Subtarget->hasThumb2())
ResNode = SelectT2IndexedLoad(Op);
ResNode = SelectT2IndexedLoad(N);
else
ResNode = SelectARMIndexedLoad(Op);
ResNode = SelectARMIndexedLoad(N);
if (ResNode)
return ResNode;
// Other cases are autogenerated.
@ -1740,11 +1735,11 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
unsigned Opc = Subtarget->isThumb() ?
((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
SDValue Chain = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
SDValue N3 = Op.getOperand(3);
SDValue InFlag = Op.getOperand(4);
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue InFlag = N->getOperand(4);
assert(N1.getOpcode() == ISD::BasicBlock);
assert(N2.getOpcode() == ISD::Constant);
assert(N3.getOpcode() == ISD::Register);
@ -1756,23 +1751,23 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
MVT::Flag, Ops, 5);
Chain = SDValue(ResNode, 0);
if (Op.getNode()->getNumValues() == 2) {
if (N->getNumValues() == 2) {
InFlag = SDValue(ResNode, 1);
ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
ReplaceUses(SDValue(N, 1), InFlag);
}
ReplaceUses(SDValue(Op.getNode(), 0),
ReplaceUses(SDValue(N, 0),
SDValue(Chain.getNode(), Chain.getResNo()));
return NULL;
}
case ARMISD::CMOV:
return SelectCMOVOp(Op);
return SelectCMOVOp(N);
case ARMISD::CNEG: {
EVT VT = Op.getValueType();
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
SDValue N3 = Op.getOperand(3);
SDValue InFlag = Op.getOperand(4);
EVT VT = N->getValueType(0);
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue InFlag = N->getOperand(4);
assert(N2.getOpcode() == ISD::Constant);
assert(N3.getOpcode() == ISD::Register);
@ -1791,7 +1786,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
Opc = ARM::VNEGDcc;
break;
}
return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
}
case ARMISD::VZIP: {
@ -1863,7 +1858,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
ARM::VLD2d32, ARM::VLD2d64 };
unsigned QOpcodes[] = { ARM::VLD2q8, ARM::VLD2q16, ARM::VLD2q32 };
return SelectVLD(Op, 2, DOpcodes, QOpcodes, 0);
return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
}
case Intrinsic::arm_neon_vld3: {
@ -1871,7 +1866,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
ARM::VLD3d32, ARM::VLD3d64 };
unsigned QOpcodes0[] = { ARM::VLD3q8a, ARM::VLD3q16a, ARM::VLD3q32a };
unsigned QOpcodes1[] = { ARM::VLD3q8b, ARM::VLD3q16b, ARM::VLD3q32b };
return SelectVLD(Op, 3, DOpcodes, QOpcodes0, QOpcodes1);
return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
}
case Intrinsic::arm_neon_vld4: {
@ -1879,35 +1874,35 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
ARM::VLD4d32, ARM::VLD4d64 };
unsigned QOpcodes0[] = { ARM::VLD4q8a, ARM::VLD4q16a, ARM::VLD4q32a };
unsigned QOpcodes1[] = { ARM::VLD4q8b, ARM::VLD4q16b, ARM::VLD4q32b };
return SelectVLD(Op, 4, DOpcodes, QOpcodes0, QOpcodes1);
return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
}
case Intrinsic::arm_neon_vld2lane: {
unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 };
unsigned QOpcodes0[] = { ARM::VLD2LNq16a, ARM::VLD2LNq32a };
unsigned QOpcodes1[] = { ARM::VLD2LNq16b, ARM::VLD2LNq32b };
return SelectVLDSTLane(Op, true, 2, DOpcodes, QOpcodes0, QOpcodes1);
return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes0, QOpcodes1);
}
case Intrinsic::arm_neon_vld3lane: {
unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 };
unsigned QOpcodes0[] = { ARM::VLD3LNq16a, ARM::VLD3LNq32a };
unsigned QOpcodes1[] = { ARM::VLD3LNq16b, ARM::VLD3LNq32b };
return SelectVLDSTLane(Op, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
}
case Intrinsic::arm_neon_vld4lane: {
unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 };
unsigned QOpcodes0[] = { ARM::VLD4LNq16a, ARM::VLD4LNq32a };
unsigned QOpcodes1[] = { ARM::VLD4LNq16b, ARM::VLD4LNq32b };
return SelectVLDSTLane(Op, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
}
case Intrinsic::arm_neon_vst2: {
unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
ARM::VST2d32, ARM::VST2d64 };
unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 };
return SelectVST(Op, 2, DOpcodes, QOpcodes, 0);
return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
}
case Intrinsic::arm_neon_vst3: {
@ -1915,7 +1910,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
ARM::VST3d32, ARM::VST3d64 };
unsigned QOpcodes0[] = { ARM::VST3q8a, ARM::VST3q16a, ARM::VST3q32a };
unsigned QOpcodes1[] = { ARM::VST3q8b, ARM::VST3q16b, ARM::VST3q32b };
return SelectVST(Op, 3, DOpcodes, QOpcodes0, QOpcodes1);
return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
}
case Intrinsic::arm_neon_vst4: {
@ -1923,34 +1918,34 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
ARM::VST4d32, ARM::VST4d64 };
unsigned QOpcodes0[] = { ARM::VST4q8a, ARM::VST4q16a, ARM::VST4q32a };
unsigned QOpcodes1[] = { ARM::VST4q8b, ARM::VST4q16b, ARM::VST4q32b };
return SelectVST(Op, 4, DOpcodes, QOpcodes0, QOpcodes1);
return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
}
case Intrinsic::arm_neon_vst2lane: {
unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 };
unsigned QOpcodes0[] = { ARM::VST2LNq16a, ARM::VST2LNq32a };
unsigned QOpcodes1[] = { ARM::VST2LNq16b, ARM::VST2LNq32b };
return SelectVLDSTLane(Op, false, 2, DOpcodes, QOpcodes0, QOpcodes1);
return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes0, QOpcodes1);
}
case Intrinsic::arm_neon_vst3lane: {
unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 };
unsigned QOpcodes0[] = { ARM::VST3LNq16a, ARM::VST3LNq32a };
unsigned QOpcodes1[] = { ARM::VST3LNq16b, ARM::VST3LNq32b };
return SelectVLDSTLane(Op, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
}
case Intrinsic::arm_neon_vst4lane: {
unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 };
unsigned QOpcodes0[] = { ARM::VST4LNq16a, ARM::VST4LNq32a };
unsigned QOpcodes1[] = { ARM::VST4LNq16b, ARM::VST4LNq32b };
return SelectVLDSTLane(Op, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
}
}
}
}
return SelectCode(Op);
return SelectCode(N);
}
bool ARMDAGToDAGISel::

4
lib/Target/ARM/ARMInstrInfo.td
View File

@ -127,8 +127,8 @@ def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
def IsARM : Predicate<"!Subtarget->isThumb()">;
def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">;
def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
def CarryDefIsUnused : Predicate<"!N->hasAnyUseOfValue(1)">;
def CarryDefIsUsed : Predicate<"N->hasAnyUseOfValue(1)">;
// FIXME: Eventually this will be just "hasV6T2Ops".
def UseMovt : Predicate<"Subtarget->useMovt()">;

26
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -157,7 +157,7 @@ namespace {
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDNode *Select(SDValue Op);
SDNode *Select(SDNode *N);
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
@ -202,7 +202,7 @@ private:
SDNode *getGlobalBaseReg();
SDNode *getGlobalRetAddr();
void SelectCALL(SDValue Op);
void SelectCALL(SDNode *Op);
};
}
@ -232,8 +232,7 @@ void AlphaDAGToDAGISel::InstructionSelect() {
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.getNode();
SDNode *AlphaDAGToDAGISel::Select(SDNode *N) {
if (N->isMachineOpcode()) {
return NULL; // Already selected.
}
@ -242,7 +241,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
switch (N->getOpcode()) {
default: break;
case AlphaISD::CALL:
SelectCALL(Op);
SelectCALL(N);
return NULL;
case ISD::FrameIndex: {
@ -258,9 +257,9 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
case AlphaISD::DivCall: {
SDValue Chain = CurDAG->getEntryNode();
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R24, N1,
SDValue(0,0));
Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R25, N2,
@ -287,7 +286,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
if (uval == 0) {
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
Alpha::R31, MVT::i64);
ReplaceUses(Op, Result);
ReplaceUses(SDValue(N, 0), Result);
return NULL;
}
@ -415,13 +414,12 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
}
return SelectCode(Op);
return SelectCode(N);
}
void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
void AlphaDAGToDAGISel::SelectCALL(SDNode *N) {
//TODO: add flag stuff to prevent nondeturministic breakage!
SDNode *N = Op.getNode();
SDValue Chain = N->getOperand(0);
SDValue Addr = N->getOperand(1);
SDValue InFlag = N->getOperand(N->getNumOperands() - 1);
@ -442,8 +440,8 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
}
InFlag = Chain.getValue(1);
ReplaceUses(Op.getValue(0), Chain);
ReplaceUses(Op.getValue(1), InFlag);
ReplaceUses(SDValue(N, 0), Chain);
ReplaceUses(SDValue(N, 1), InFlag);
}

11
lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
View File

@ -51,8 +51,8 @@ namespace {
#include "BlackfinGenDAGISel.inc"
private:
SDNode *Select(SDValue Op);
bool SelectADDRspii(SDValue Op, SDValue Addr,
SDNode *Select(SDNode *N);
bool SelectADDRspii(SDNode *Op, SDValue Addr,
SDValue &Base, SDValue &Offset);
// Walk the DAG after instruction selection, fixing register class issues.
@ -82,8 +82,7 @@ void BlackfinDAGToDAGISel::InstructionSelect() {
FixRegisterClasses(*CurDAG);
}
SDNode *BlackfinDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.getNode();
SDNode *BlackfinDAGToDAGISel::Select(SDNode *N) {
if (N->isMachineOpcode())
return NULL; // Already selected.
@ -99,10 +98,10 @@ SDNode *BlackfinDAGToDAGISel::Select(SDValue Op) {
}
}
return SelectCode(Op);
return SelectCode(N);
}
bool BlackfinDAGToDAGISel::SelectADDRspii(SDValue Op,
bool BlackfinDAGToDAGISel::SelectADDRspii(SDNode *Op,
SDValue Addr,
SDValue &Base,
SDValue &Offset) {

171
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -277,10 +277,9 @@ namespace {
return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
}
SDNode *emitBuildVector(SDValue build_vec) {
EVT vecVT = build_vec.getValueType();
SDNode *emitBuildVector(SDNode *bvNode) {
EVT vecVT = bvNode->getValueType(0);
EVT eltVT = vecVT.getVectorElementType();
SDNode *bvNode = build_vec.getNode();
DebugLoc dl = bvNode->getDebugLoc();
// Check to see if this vector can be represented as a CellSPU immediate
@ -296,13 +295,13 @@ namespace {
((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
(SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
(SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0))))
return Select(build_vec);
return Select(bvNode);
// No, need to emit a constant pool spill:
std::vector<Constant*> CV;
for (size_t i = 0; i < build_vec.getNumOperands(); ++i) {
ConstantSDNode *V = dyn_cast<ConstantSDNode > (build_vec.getOperand(i));
for (size_t i = 0; i < bvNode->getNumOperands(); ++i) {
ConstantSDNode *V = dyn_cast<ConstantSDNode > (bvNode->getOperand(i));
CV.push_back(const_cast<ConstantInt *> (V->getConstantIntValue()));
}
@ -312,49 +311,49 @@ namespace {
SDValue CGPoolOffset =
SPU::LowerConstantPool(CPIdx, *CurDAG,
SPUtli.getSPUTargetMachine());
return SelectCode(CurDAG->getLoad(build_vec.getValueType(), dl,
return SelectCode(CurDAG->getLoad(vecVT, dl,
CurDAG->getEntryNode(), CGPoolOffset,
PseudoSourceValue::getConstantPool(), 0,
false, Alignment));
false, Alignment).getNode());
}
/// Select - Convert the specified operand from a target-independent to a
/// target-specific node if it hasn't already been changed.
SDNode *Select(SDValue Op);
SDNode *Select(SDNode *N);
//! Emit the instruction sequence for i64 shl
SDNode *SelectSHLi64(SDValue &Op, EVT OpVT);
SDNode *SelectSHLi64(SDNode *N, EVT OpVT);
//! Emit the instruction sequence for i64 srl
SDNode *SelectSRLi64(SDValue &Op, EVT OpVT);
SDNode *SelectSRLi64(SDNode *N, EVT OpVT);
//! Emit the instruction sequence for i64 sra
SDNode *SelectSRAi64(SDValue &Op, EVT OpVT);
SDNode *SelectSRAi64(SDNode *N, EVT OpVT);
//! Emit the necessary sequence for loading i64 constants:
SDNode *SelectI64Constant(SDValue &Op, EVT OpVT, DebugLoc dl);
SDNode *SelectI64Constant(SDNode *N, EVT OpVT, DebugLoc dl);
//! Alternate instruction emit sequence for loading i64 constants
SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
//! Returns true if the address N is an A-form (local store) address
bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
bool SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Index);
//! D-form address predicate
bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
bool SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Index);
/// Alternate D-form address using i7 offset predicate
bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
bool SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
SDValue &Base);
/// D-form address selection workhorse
bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
bool DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Disp,
SDValue &Base, int minOffset, int maxOffset);
//! Address predicate if N can be expressed as an indexed [r+r] operation.
bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
bool SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Index);
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
@ -366,13 +365,13 @@ namespace {
switch (ConstraintCode) {
default: return true;
case 'm': // memory
if (!SelectDFormAddr(Op, Op, Op0, Op1)
&& !SelectAFormAddr(Op, Op, Op0, Op1))
SelectXFormAddr(Op, Op, Op0, Op1);
if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
&& !SelectAFormAddr(Op.getNode(), Op, Op0, Op1))
SelectXFormAddr(Op.getNode(), Op, Op0, Op1);
break;
case 'o': // offsetable
if (!SelectDFormAddr(Op, Op, Op0, Op1)
&& !SelectAFormAddr(Op, Op, Op0, Op1)) {
if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
&& !SelectAFormAddr(Op.getNode(), Op, Op0, Op1)) {
Op0 = Op;
Op1 = getSmallIPtrImm(0);
}
@ -429,7 +428,7 @@ SPUDAGToDAGISel::InstructionSelect()
\arg Index The base address index
*/
bool
SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
SPUDAGToDAGISel::SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Index) {
// These match the addr256k operand type:
EVT OffsVT = MVT::i16;
@ -479,7 +478,7 @@ SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
}
bool
SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
SPUDAGToDAGISel::SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
SDValue &Base) {
const int minDForm2Offset = -(1 << 7);
const int maxDForm2Offset = (1 << 7) - 1;
@ -500,7 +499,7 @@ SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
to non-empty SDValue instances.
*/
bool
SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
SPUDAGToDAGISel::SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Index) {
return DFormAddressPredicate(Op, N, Base, Index,
SPUFrameInfo::minFrameOffset(),
@ -508,7 +507,7 @@ SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
}
bool
SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Index, int minOffset,
int maxOffset) {
unsigned Opc = N.getOpcode();
@ -618,7 +617,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
Index = N;
return true;
} else if (Opc == ISD::Register || Opc == ISD::CopyFromReg) {
unsigned OpOpc = Op.getOpcode();
unsigned OpOpc = Op->getOpcode();
if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
// Direct load/store without getelementptr
@ -630,7 +629,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
else
Addr = N; // Register
Offs = ((OpOpc == ISD::STORE) ? Op.getOperand(3) : Op.getOperand(2));
Offs = ((OpOpc == ISD::STORE) ? Op->getOperand(3) : Op->getOperand(2));
if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
if (Offs.getOpcode() == ISD::UNDEF)
@ -667,7 +666,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
(r)(r) X-form address.
*/
bool
SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
SPUDAGToDAGISel::SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Index) {
if (!SelectAFormAddr(Op, N, Base, Index)
&& !SelectDFormAddr(Op, N, Base, Index)) {
@ -685,12 +684,11 @@ SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
/*!
*/
SDNode *
SPUDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.getNode();
SPUDAGToDAGISel::Select(SDNode *N) {
unsigned Opc = N->getOpcode();
int n_ops = -1;
unsigned NewOpc;
EVT OpVT = Op.getValueType();
EVT OpVT = N->getValueType(0);
SDValue Ops[8];
DebugLoc dl = N->getDebugLoc();
@ -700,8 +698,8 @@ SPUDAGToDAGISel::Select(SDValue Op) {
if (Opc == ISD::FrameIndex) {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
SDValue Imm0 = CurDAG->getTargetConstant(0, Op.getValueType());
SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
SDValue Imm0 = CurDAG->getTargetConstant(0, N->getValueType(0));
if (FI < 128) {
NewOpc = SPU::AIr32;
@ -710,9 +708,9 @@ SPUDAGToDAGISel::Select(SDValue Op) {
n_ops = 2;
} else {
NewOpc = SPU::Ar32;
Ops[0] = CurDAG->getRegister(SPU::R1, Op.getValueType());
Ops[0] = CurDAG->getRegister(SPU::R1, N->getValueType(0));
Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILAr32, dl,
Op.getValueType(), TFI, Imm0),
N->getValueType(0), TFI, Imm0),
0);
n_ops = 2;
}
@ -720,10 +718,10 @@ SPUDAGToDAGISel::Select(SDValue Op) {
// Catch the i64 constants that end up here. Note: The backend doesn't
// attempt to legalize the constant (it's useless because DAGCombiner
// will insert 64-bit constants and we can't stop it).
return SelectI64Constant(Op, OpVT, Op.getDebugLoc());
return SelectI64Constant(N, OpVT, N->getDebugLoc());
} else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
&& OpVT == MVT::i64) {
SDValue Op0 = Op.getOperand(0);
SDValue Op0 = N->getOperand(0);
EVT Op0VT = Op0.getValueType();
EVT Op0VecVT = EVT::getVectorVT(*CurDAG->getContext(),
Op0VT, (128 / Op0VT.getSizeInBits()));
@ -760,9 +758,10 @@ SPUDAGToDAGISel::Select(SDValue Op) {
break;
}
SDNode *shufMaskLoad = emitBuildVector(shufMask);
SDNode *shufMaskLoad = emitBuildVector(shufMask.getNode());
SDNode *PromoteScalar =
SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl, Op0VecVT, Op0));
SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl,
Op0VecVT, Op0).getNode());
SDValue zextShuffle =
CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
@ -773,32 +772,32 @@ SPUDAGToDAGISel::Select(SDValue Op) {
// N.B.: BIT_CONVERT replaces and updates the zextShuffle node, so we
// re-use it in the VEC2PREFSLOT selection without needing to explicitly
// call SelectCode (it's already done for us.)
SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, dl, OpVecVT, zextShuffle));
SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, dl, OpVecVT, zextShuffle).getNode());
return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
zextShuffle));
zextShuffle).getNode());
} else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl));
emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
Op.getOperand(0), Op.getOperand(1),
SDValue(CGLoad, 0)));
N->getOperand(0), N->getOperand(1),
SDValue(CGLoad, 0)).getNode());
} else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl));
emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl).getNode());
return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
Op.getOperand(0), Op.getOperand(1),
SDValue(CGLoad, 0)));
N->getOperand(0), N->getOperand(1),
SDValue(CGLoad, 0)).getNode());
} else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl));
emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT,
Op.getOperand(0), Op.getOperand(1),
SDValue(CGLoad, 0)));
N->getOperand(0), N->getOperand(1),
SDValue(CGLoad, 0)).getNode());
} else if (Opc == ISD::TRUNCATE) {
SDValue Op0 = Op.getOperand(0);
SDValue Op0 = N->getOperand(0);
if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
&& OpVT == MVT::i32
&& Op0.getValueType() == MVT::i64) {
@ -834,22 +833,22 @@ SPUDAGToDAGISel::Select(SDValue Op) {
}
} else if (Opc == ISD::SHL) {
if (OpVT == MVT::i64) {
return SelectSHLi64(Op, OpVT);
return SelectSHLi64(N, OpVT);
}
} else if (Opc == ISD::SRL) {
if (OpVT == MVT::i64) {
return SelectSRLi64(Op, OpVT);
return SelectSRLi64(N, OpVT);
}
} else if (Opc == ISD::SRA) {
if (OpVT == MVT::i64) {
return SelectSRAi64(Op, OpVT);
return SelectSRAi64(N, OpVT);
}
} else if (Opc == ISD::FNEG
&& (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
DebugLoc dl = Op.getDebugLoc();
DebugLoc dl = N->getDebugLoc();
// Check if the pattern is a special form of DFNMS:
// (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
SDValue Op0 = Op.getOperand(0);
SDValue Op0 = N->getOperand(0);
if (Op0.getOpcode() == ISD::FSUB) {
SDValue Op00 = Op0.getOperand(0);
if (Op00.getOpcode() == ISD::FMUL) {
@ -869,28 +868,28 @@ SPUDAGToDAGISel::Select(SDValue Op) {
unsigned Opc = SPU::XORfneg64;
if (OpVT == MVT::f64) {
signMask = SelectI64Constant(negConst, MVT::i64, dl);
signMask = SelectI64Constant(negConst.getNode(), MVT::i64, dl);
} else if (OpVT == MVT::v2f64) {
Opc = SPU::XORfnegvec;
signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
MVT::v2i64,
negConst, negConst));
negConst, negConst).getNode());
}
return CurDAG->getMachineNode(Opc, dl, OpVT,
Op.getOperand(0), SDValue(signMask, 0));
N->getOperand(0), SDValue(signMask, 0));
} else if (Opc == ISD::FABS) {
if (OpVT == MVT::f64) {
SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
return CurDAG->getMachineNode(SPU::ANDfabs64, dl, OpVT,
Op.getOperand(0), SDValue(signMask, 0));
N->getOperand(0), SDValue(signMask, 0));
} else if (OpVT == MVT::v2f64) {
SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
absConst, absConst);
SDNode *signMask = emitBuildVector(absVec);
SDNode *signMask = emitBuildVector(absVec.getNode());
return CurDAG->getMachineNode(SPU::ANDfabsvec, dl, OpVT,
Op.getOperand(0), SDValue(signMask, 0));
N->getOperand(0), SDValue(signMask, 0));
}
} else if (Opc == SPUISD::LDRESULT) {
// Custom select instructions for LDRESULT
@ -925,7 +924,7 @@ SPUDAGToDAGISel::Select(SDValue Op) {
// SPUInstrInfo catches the following patterns:
// (SPUindirect (SPUhi ...), (SPUlo ...))
// (SPUindirect $sp, imm)
EVT VT = Op.getValueType();
EVT VT = N->getValueType(0);
SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
RegisterSDNode *RN;
@ -952,7 +951,7 @@ SPUDAGToDAGISel::Select(SDValue Op) {
else
return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops);
} else
return SelectCode(Op);
return SelectCode(N);
}
/*!
@ -968,15 +967,15 @@ SPUDAGToDAGISel::Select(SDValue Op) {
* @return The SDNode with the entire instruction sequence
*/
SDNode *
SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, EVT OpVT) {
SDValue Op0 = Op.getOperand(0);
SPUDAGToDAGISel::SelectSHLi64(SDNode *N, EVT OpVT) {
SDValue Op0 = N->getOperand(0);
EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
OpVT, (128 / OpVT.getSizeInBits()));
SDValue ShiftAmt = Op.getOperand(1);
SDValue ShiftAmt = N->getOperand(1);
EVT ShiftAmtVT = ShiftAmt.getValueType();
SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
SDValue SelMaskVal;
DebugLoc dl = Op.getDebugLoc();
DebugLoc dl = N->getDebugLoc();
VecOp0 = CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
@ -1034,14 +1033,14 @@ SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, EVT OpVT) {
* @return The SDNode with the entire instruction sequence
*/
SDNode *
SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, EVT OpVT) {
SDValue Op0 = Op.getOperand(0);
SPUDAGToDAGISel::SelectSRLi64(SDNode *N, EVT OpVT) {
SDValue Op0 = N->getOperand(0);
EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
OpVT, (128 / OpVT.getSizeInBits()));
SDValue ShiftAmt = Op.getOperand(1);
SDValue ShiftAmt = N->getOperand(1);
EVT ShiftAmtVT = ShiftAmt.getValueType();
SDNode *VecOp0, *Shift = 0;
DebugLoc dl = Op.getDebugLoc();
DebugLoc dl = N->getDebugLoc();
VecOp0 = CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
@ -1101,16 +1100,16 @@ SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, EVT OpVT) {
* @return The SDNode with the entire instruction sequence
*/
SDNode *
SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, EVT OpVT) {
SPUDAGToDAGISel::SelectSRAi64(SDNode *N, EVT OpVT) {
// Promote Op0 to vector
EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
OpVT, (128 / OpVT.getSizeInBits()));
SDValue ShiftAmt = Op.getOperand(1);
SDValue ShiftAmt = N->getOperand(1);
EVT ShiftAmtVT = ShiftAmt.getValueType();
DebugLoc dl = Op.getDebugLoc();
DebugLoc dl = N->getDebugLoc();
SDNode *VecOp0 =
CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op.getOperand(0));
CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, N->getOperand(0));
SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
SDNode *SignRot =
@ -1170,9 +1169,9 @@ SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, EVT OpVT) {
/*!
Do the necessary magic necessary to load a i64 constant
*/
SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, EVT OpVT,
SDNode *SPUDAGToDAGISel::SelectI64Constant(SDNode *N, EVT OpVT,
DebugLoc dl) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
ConstantSDNode *CN = cast<ConstantSDNode>(N);
return SelectI64Constant(CN->getZExtValue(), OpVT, dl);
}
@ -1192,7 +1191,7 @@ SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
ReplaceUses(i64vec, Op0);
return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT,
SDValue(emitBuildVector(Op0), 0));
SDValue(emitBuildVector(Op0.getNode()), 0));
} else if (i64vec.getOpcode() == SPUISD::SHUFB) {
SDValue lhs = i64vec.getOperand(0);
SDValue rhs = i64vec.getOperand(1);
@ -1205,7 +1204,7 @@ SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
? lhs.getNode()
: emitBuildVector(lhs));
: emitBuildVector(lhs.getNode()));
if (rhs.getOpcode() == ISD::BIT_CONVERT) {
ReplaceUses(rhs, rhs.getOperand(0));
@ -1214,7 +1213,7 @@ SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
? rhs.getNode()
: emitBuildVector(rhs));
: emitBuildVector(rhs.getNode()));
if (shufmask.getOpcode() == ISD::BIT_CONVERT) {
ReplaceUses(shufmask, shufmask.getOperand(0));
@ -1223,18 +1222,18 @@ SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
? shufmask.getNode()
: emitBuildVector(shufmask));
: emitBuildVector(shufmask.getNode()));
SDNode *shufNode =
Select(CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
SDValue(lhsNode, 0), SDValue(rhsNode, 0),
SDValue(shufMaskNode, 0)));
SDValue(shufMaskNode, 0)).getNode());
return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT,
SDValue(shufNode, 0));
} else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) {
return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT,
SDValue(emitBuildVector(i64vec), 0));
SDValue(emitBuildVector(i64vec.getNode()), 0));
} else {
llvm_report_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec"
"condition");

67
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
View File

@ -146,12 +146,12 @@ namespace {
private:
DenseMap<SDNode*, SDNode*> RMWStores;
void PreprocessForRMW();
SDNode *Select(SDValue Op);
SDNode *SelectIndexedLoad(SDValue Op);
SDNode *SelectIndexedBinOp(SDValue Op, SDValue N1, SDValue N2,
SDNode *Select(SDNode *N);
SDNode *SelectIndexedLoad(SDNode *Op);
SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
unsigned Opc8, unsigned Opc16);
bool SelectAddr(SDValue Op, SDValue Addr, SDValue &Base, SDValue &Disp);
bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Disp);
#ifndef NDEBUG
unsigned Indent;
@ -283,7 +283,7 @@ bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
/// SelectAddr - returns true if it is able pattern match an addressing mode.
/// It returns the operands which make up the maximal addressing mode it can
/// match by reference.
bool MSP430DAGToDAGISel::SelectAddr(SDValue Op, SDValue N,
bool MSP430DAGToDAGISel::SelectAddr(SDNode *Op, SDValue N,
SDValue &Base, SDValue &Disp) {
MSP430ISelAddressMode AM;
@ -326,7 +326,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
switch (ConstraintCode) {
default: return true;
case 'm': // memory
if (!SelectAddr(Op, Op, Op0, Op1))
if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
return true;
break;
}
@ -627,8 +627,8 @@ static bool isValidIndexedLoad(const LoadSDNode *LD) {
return true;
}
SDNode *MSP430DAGToDAGISel::SelectIndexedLoad(SDValue Op) {
LoadSDNode *LD = cast<LoadSDNode>(Op);
SDNode *MSP430DAGToDAGISel::SelectIndexedLoad(SDNode *N) {
LoadSDNode *LD = cast<LoadSDNode>(N);
if (!isValidIndexedLoad(LD))
return NULL;
@ -646,17 +646,17 @@ SDNode *MSP430DAGToDAGISel::SelectIndexedLoad(SDValue Op) {
return NULL;
}
return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(),
return CurDAG->getMachineNode(Opcode, N->getDebugLoc(),
VT, MVT::i16, MVT::Other,
LD->getBasePtr(), LD->getChain());
}
SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDValue Op,
SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op,
SDValue N1, SDValue N2,
unsigned Opc8, unsigned Opc16) {
if (N1.getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), Op.getNode(), Op.getNode())) {
IsLegalAndProfitableToFold(N1.getNode(), Op, Op)) {
LoadSDNode *LD = cast<LoadSDNode>(N1);
if (!isValidIndexedLoad(LD))
return NULL;
@ -667,7 +667,7 @@ SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDValue Op,
MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
SDNode *ResNode =
CurDAG->SelectNodeTo(Op.getNode(), Opc,
CurDAG->SelectNodeTo(Op, Opc,
VT, MVT::i16, MVT::Other,
Ops0, 3);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
@ -707,9 +707,8 @@ void MSP430DAGToDAGISel::InstructionSelect() {
RMWStores.clear();
}
SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
SDNode *Node = Op.getNode();
DebugLoc dl = Op.getDebugLoc();
SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) {
DebugLoc dl = Node->getDebugLoc();
// Dump information about the Node being selected
DEBUG(errs().indent(Indent) << "Selecting: ");
@ -730,7 +729,7 @@ SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
switch (Node->getOpcode()) {
default: break;
case ISD::FrameIndex: {
assert(Op.getValueType() == MVT::i16);
assert(Node->getValueType(0) == MVT::i16);
int FI = cast<FrameIndexSDNode>(Node)->getIndex();
SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
if (Node->hasOneUse())
@ -740,18 +739,18 @@ SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
TFI, CurDAG->getTargetConstant(0, MVT::i16));
}
case ISD::LOAD:
if (SDNode *ResNode = SelectIndexedLoad(Op))
if (SDNode *ResNode = SelectIndexedLoad(Node))
return ResNode;
// Other cases are autogenerated.
break;
case ISD::ADD:
if (SDNode *ResNode =
SelectIndexedBinOp(Op,
Op.getOperand(0), Op.getOperand(1),
SelectIndexedBinOp(Node,
Node->getOperand(0), Node->getOperand(1),
MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
return ResNode;
else if (SDNode *ResNode =
SelectIndexedBinOp(Op, Op.getOperand(1), Op.getOperand(0),
SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
return ResNode;
@ -759,8 +758,8 @@ SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
break;
case ISD::SUB:
if (SDNode *ResNode =
SelectIndexedBinOp(Op,
Op.getOperand(0), Op.getOperand(1),
SelectIndexedBinOp(Node,
Node->getOperand(0), Node->getOperand(1),
MSP430::SUB8rm_POST, MSP430::SUB16rm_POST))
return ResNode;
@ -768,12 +767,12 @@ SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
break;
case ISD::AND:
if (SDNode *ResNode =
SelectIndexedBinOp(Op,
Op.getOperand(0), Op.getOperand(1),
SelectIndexedBinOp(Node,
Node->getOperand(0), Node->getOperand(1),
MSP430::AND8rm_POST, MSP430::AND16rm_POST))
return ResNode;
else if (SDNode *ResNode =
SelectIndexedBinOp(Op, Op.getOperand(1), Op.getOperand(0),
SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
MSP430::AND8rm_POST, MSP430::AND16rm_POST))
return ResNode;
@ -781,12 +780,12 @@ SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
break;
case ISD::OR:
if (SDNode *ResNode =
SelectIndexedBinOp(Op,
Op.getOperand(0), Op.getOperand(1),
SelectIndexedBinOp(Node,
Node->getOperand(0), Node->getOperand(1),
MSP430::OR8rm_POST, MSP430::OR16rm_POST))
return ResNode;
else if (SDNode *ResNode =
SelectIndexedBinOp(Op, Op.getOperand(1), Op.getOperand(0),
SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
MSP430::OR8rm_POST, MSP430::OR16rm_POST))
return ResNode;
@ -794,12 +793,12 @@ SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
break;
case ISD::XOR:
if (SDNode *ResNode =
SelectIndexedBinOp(Op,
Op.getOperand(0), Op.getOperand(1),
SelectIndexedBinOp(Node,
Node->getOperand(0), Node->getOperand(1),
MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
return ResNode;
else if (SDNode *ResNode =
SelectIndexedBinOp(Op, Op.getOperand(1), Op.getOperand(0),
SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
return ResNode;
@ -808,11 +807,11 @@ SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
}
// Select the default instruction
SDNode *ResNode = SelectCode(Op);
SDNode *ResNode = SelectCode(Node);
DEBUG(errs() << std::string(Indent-2, ' ') << "=> ");
if (ResNode == NULL || ResNode == Op.getNode())
DEBUG(Op.getNode()->dump(CurDAG));
if (ResNode == NULL || ResNode == Node)
DEBUG(Node->dump(CurDAG));
else
DEBUG(ResNode->dump(CurDAG));
DEBUG(errs() << "\n");

75
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -84,14 +84,14 @@ private:
}
SDNode *getGlobalBaseReg();
SDNode *Select(SDValue N);
SDNode *Select(SDNode *N);
// Complex Pattern.
bool SelectAddr(SDValue Op, SDValue N,
bool SelectAddr(SDNode *Op, SDValue N,
SDValue &Base, SDValue &Offset);
SDNode *SelectLoadFp64(SDValue N);
SDNode *SelectStoreFp64(SDValue N);
SDNode *SelectLoadFp64(SDNode *N);
SDNode *SelectStoreFp64(SDNode *N);
// getI32Imm - Return a target constant with the specified
// value, of type i32.
@ -132,7 +132,7 @@ SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
/// ComplexPattern used on MipsInstrInfo
/// Used on Mips Load/Store instructions
bool MipsDAGToDAGISel::
SelectAddr(SDValue Op, SDValue Addr, SDValue &Offset, SDValue &Base)
SelectAddr(SDNode *Op, SDValue Addr, SDValue &Offset, SDValue &Base)
{
// if Address is FI, get the TargetFrameIndex.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
@ -199,19 +199,19 @@ SelectAddr(SDValue Op, SDValue Addr, SDValue &Offset, SDValue &Base)
return true;
}
SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDValue N) {
SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
MVT::SimpleValueType NVT =
N.getNode()->getValueType(0).getSimpleVT().SimpleTy;
N->getValueType(0).getSimpleVT().SimpleTy;
if (!Subtarget.isMips1() || NVT != MVT::f64)
return NULL;
if (!Predicate_unindexedload(N.getNode()) ||
!Predicate_load(N.getNode()))
if (!Predicate_unindexedload(N) ||
!Predicate_load(N))
return NULL;
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Offset0, Offset1, Base;
if (!SelectAddr(N, N1, Offset0, Base) ||
@ -220,7 +220,7 @@ SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDValue N) {
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
DebugLoc dl = N.getDebugLoc();
DebugLoc dl = N->getDebugLoc();
// The second load should start after for 4 bytes.
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
@ -255,27 +255,27 @@ SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDValue N) {
SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPODD, dl,
MVT::f64, I0, SDValue(LD1, 0));
ReplaceUses(N, I1);
ReplaceUses(N.getValue(1), Chain);
ReplaceUses(SDValue(N, 0), I1);
ReplaceUses(SDValue(N, 1), Chain);
cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
return I1.getNode();
}
SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDValue N) {
SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
if (!Subtarget.isMips1() ||
N.getOperand(1).getValueType() != MVT::f64)
N->getOperand(1).getValueType() != MVT::f64)
return NULL;
SDValue Chain = N.getOperand(0);
SDValue Chain = N->getOperand(0);
if (!Predicate_unindexedstore(N.getNode()) ||
!Predicate_store(N.getNode()))
if (!Predicate_unindexedstore(N) ||
!Predicate_store(N))
return NULL;
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue Offset0, Offset1, Base;
if (!SelectAddr(N, N2, Offset0, Base) ||
@ -285,7 +285,7 @@ SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDValue N) {
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
DebugLoc dl = N.getDebugLoc();
DebugLoc dl = N->getDebugLoc();
// Get the even and odd part from the f64 register
SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::SUBREG_FPODD,
@ -318,14 +318,13 @@ SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDValue N) {
MVT::Other, Ops1, 4), 0);
cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(N.getValue(0), Chain);
ReplaceUses(SDValue(N, 0), Chain);
return Chain.getNode();
}
/// Select instructions not customized! Used for
/// expanded, promoted and normal instructions
SDNode* MipsDAGToDAGISel::Select(SDValue N) {
SDNode *Node = N.getNode();
SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
unsigned Opcode = Node->getOpcode();
DebugLoc dl = Node->getDebugLoc();
@ -379,7 +378,7 @@ SDNode* MipsDAGToDAGISel::Select(SDValue N) {
SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
SDValue(Carry,0), RHS);
return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag,
return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Flag,
LHS, SDValue(AddCarry,0));
}
@ -405,11 +404,11 @@ SDNode* MipsDAGToDAGISel::Select(SDValue N) {
InFlag = SDValue(Lo,1);
SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
if (!N.getValue(0).use_empty())
ReplaceUses(N.getValue(0), SDValue(Lo,0));
if (!SDValue(Node, 0).use_empty())
ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
if (!N.getValue(1).use_empty())
ReplaceUses(N.getValue(1), SDValue(Hi,0));
if (!SDValue(Node, 1).use_empty())
ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
return NULL;
}
@ -460,23 +459,23 @@ SDNode* MipsDAGToDAGISel::Select(SDValue N) {
return getGlobalBaseReg();
case ISD::ConstantFP: {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
if (N.getValueType() == MVT::f64 && CN->isExactlyValue(+0.0)) {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
ReplaceUses(N, Zero);
ReplaceUses(SDValue(Node, 0), Zero);
return Zero.getNode();
}
break;
}
case ISD::LOAD:
if (SDNode *ResNode = SelectLoadFp64(N))
if (SDNode *ResNode = SelectLoadFp64(Node))
return ResNode;
// Other cases are autogenerated.
break;
case ISD::STORE:
if (SDNode *ResNode = SelectStoreFp64(N))
if (SDNode *ResNode = SelectStoreFp64(Node))
return ResNode;
// Other cases are autogenerated.
break;
@ -523,11 +522,11 @@ SDNode* MipsDAGToDAGISel::Select(SDValue N) {
}
// Select the default instruction
SDNode *ResNode = SelectCode(N);
SDNode *ResNode = SelectCode(Node);
DEBUG(errs().indent(Indent-2) << "=> ");
if (ResNode == NULL || ResNode == N.getNode())
DEBUG(N.getNode()->dump(CurDAG));
if (ResNode == NULL || ResNode == Node)
DEBUG(Node->dump(CurDAG));
else
DEBUG(ResNode->dump(CurDAG));
DEBUG(errs() << "\n");

4
lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
View File

@ -36,7 +36,7 @@ void PIC16DAGToDAGISel::InstructionSelect() {
/// Select - Select instructions not customized! Used for
/// expanded, promoted and normal instructions.
SDNode* PIC16DAGToDAGISel::Select(SDValue N) {
SDNode* PIC16DAGToDAGISel::Select(SDNode *N) {
// Select the default instruction.
SDNode *ResNode = SelectCode(N);
@ -47,7 +47,7 @@ SDNode* PIC16DAGToDAGISel::Select(SDValue N) {
// SelectDirectAddr - Match a direct address for DAG.
// A direct address could be a globaladdress or externalsymbol.
bool PIC16DAGToDAGISel::SelectDirectAddr(SDValue Op, SDValue N,
bool PIC16DAGToDAGISel::SelectDirectAddr(SDNode *Op, SDValue N,
SDValue &Address) {
// Return true if TGA or ES.
if (N.getOpcode() == ISD::TargetGlobalAddress

4
lib/Target/PIC16/PIC16ISelDAGToDAG.h
View File

@ -52,10 +52,10 @@ private:
// Include the pieces autogenerated from the target description.
#include "PIC16GenDAGISel.inc"
SDNode *Select(SDValue N);
SDNode *Select(SDNode *N);
// Match direct address complex pattern.
bool SelectDirectAddr(SDValue Op, SDValue N, SDValue &Address);
bool SelectDirectAddr(SDNode *Op, SDValue N, SDValue &Address);
};

36
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -95,7 +95,7 @@ namespace {
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDNode *Select(SDValue Op);
SDNode *Select(SDNode *N);
SDNode *SelectBitfieldInsert(SDNode *N);
@ -105,7 +105,7 @@ namespace {
/// SelectAddrImm - Returns true if the address N can be represented by
/// a base register plus a signed 16-bit displacement [r+imm].
bool SelectAddrImm(SDValue Op, SDValue N, SDValue &Disp,
bool SelectAddrImm(SDNode *Op, SDValue N, SDValue &Disp,
SDValue &Base) {
return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
}
@ -113,7 +113,7 @@ namespace {
/// SelectAddrImmOffs - Return true if the operand is valid for a preinc
/// immediate field. Because preinc imms have already been validated, just
/// accept it.
bool SelectAddrImmOffs(SDValue Op, SDValue N, SDValue &Out) const {
bool SelectAddrImmOffs(SDNode *Op, SDValue N, SDValue &Out) const {
Out = N;
return true;
}
@ -121,14 +121,14 @@ namespace {
/// SelectAddrIdx - Given the specified addressed, check to see if it can be
/// represented as an indexed [r+r] operation. Returns false if it can
/// be represented by [r+imm], which are preferred.
bool SelectAddrIdx(SDValue Op, SDValue N, SDValue &Base,
bool SelectAddrIdx(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Index) {
return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
}
/// SelectAddrIdxOnly - Given the specified addressed, force it to be
/// represented as an indexed [r+r] operation.
bool SelectAddrIdxOnly(SDValue Op, SDValue N, SDValue &Base,
bool SelectAddrIdxOnly(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Index) {
return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
}
@ -136,7 +136,7 @@ namespace {
/// SelectAddrImmShift - Returns true if the address N can be represented by
/// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
/// for use by STD and friends.
bool SelectAddrImmShift(SDValue Op, SDValue N, SDValue &Disp,
bool SelectAddrImmShift(SDNode *Op, SDValue N, SDValue &Disp,
SDValue &Base) {
return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
}
@ -180,7 +180,7 @@ namespace {
#include "PPCGenDAGISel.inc"
private:
SDNode *SelectSETCC(SDValue Op);
SDNode *SelectSETCC(SDNode *N);
};
}
@ -635,8 +635,7 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
return 0;
}
SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
SDNode *N = Op.getNode();
SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
unsigned Imm;
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
@ -756,9 +755,8 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.getNode();
DebugLoc dl = Op.getDebugLoc();
SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
if (N->isMachineOpcode())
return NULL; // Already selected.
@ -841,18 +839,18 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
}
case ISD::SETCC:
return SelectSETCC(Op);
return SelectSETCC(N);
case PPCISD::GlobalBaseReg:
return getGlobalBaseReg();
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
if (N->hasOneUse())
return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI,
getSmallIPtrImm(0));
return CurDAG->getMachineNode(Opc, dl, Op.getValueType(), TFI,
return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
getSmallIPtrImm(0));
}
@ -899,7 +897,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
case ISD::LOAD: {
// Handle preincrement loads.
LoadSDNode *LD = cast<LoadSDNode>(Op);
LoadSDNode *LD = cast<LoadSDNode>(N);
EVT LoadedVT = LD->getMemoryVT();
// Normal loads are handled by code generated from the .td file.
@ -1092,7 +1090,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
}
}
return SelectCode(Op);
return SelectCode(N);
}

19
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -43,11 +43,11 @@ public:
TM(tm) {
}
SDNode *Select(SDValue Op);
SDNode *Select(SDNode *N);
// Complex Pattern Selectors.
bool SelectADDRrr(SDValue Op, SDValue N, SDValue &R1, SDValue &R2);
bool SelectADDRri(SDValue Op, SDValue N, SDValue &Base,
bool SelectADDRrr(SDNode *Op, SDValue N, SDValue &R1, SDValue &R2);
bool SelectADDRri(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Offset);
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
@ -87,7 +87,7 @@ SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
}
bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
bool SparcDAGToDAGISel::SelectADDRri(SDNode *Op, SDValue Addr,
SDValue &Base, SDValue &Offset) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
@ -128,7 +128,7 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
return true;
}
bool SparcDAGToDAGISel::SelectADDRrr(SDValue Op, SDValue Addr,
bool SparcDAGToDAGISel::SelectADDRrr(SDNode *Op, SDValue Addr,
SDValue &R1, SDValue &R2) {
if (Addr.getOpcode() == ISD::FrameIndex) return false;
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
@ -152,8 +152,7 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDValue Op, SDValue Addr,
return true;
}
SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.getNode();
SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
if (N->isMachineOpcode())
return NULL; // Already selected.
@ -199,7 +198,7 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
}
}
return SelectCode(Op);
return SelectCode(N);
}
@ -213,8 +212,8 @@ SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
switch (ConstraintCode) {
default: return true;
case 'm': // memory
if (!SelectADDRrr(Op, Op, Op0, Op1))
SelectADDRri(Op, Op, Op0, Op1);
if (!SelectADDRrr(Op.getNode(), Op, Op0, Op1))
SelectADDRri(Op.getNode(), Op, Op0, Op1);
break;
}

63
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -128,23 +128,23 @@ namespace {
#include "SystemZGenDAGISel.inc"
private:
bool SelectAddrRI12Only(SDValue Op, SDValue& Addr,
bool SelectAddrRI12Only(SDNode *Op, SDValue& Addr,
SDValue &Base, SDValue &Disp);
bool SelectAddrRI12(SDValue Op, SDValue& Addr,
bool SelectAddrRI12(SDNode *Op, SDValue& Addr,
SDValue &Base, SDValue &Disp,
bool is12BitOnly = false);
bool SelectAddrRI(SDValue Op, SDValue& Addr,
bool SelectAddrRI(SDNode *Op, SDValue& Addr,
SDValue &Base, SDValue &Disp);
bool SelectAddrRRI12(SDValue Op, SDValue Addr,
bool SelectAddrRRI12(SDNode *Op, SDValue Addr,
SDValue &Base, SDValue &Disp, SDValue &Index);
bool SelectAddrRRI20(SDValue Op, SDValue Addr,
bool SelectAddrRRI20(SDNode *Op, SDValue Addr,
SDValue &Base, SDValue &Disp, SDValue &Index);
bool SelectLAAddr(SDValue Op, SDValue Addr,
bool SelectLAAddr(SDNode *Op, SDValue Addr,
SDValue &Base, SDValue &Disp, SDValue &Index);
SDNode *Select(SDValue Op);
SDNode *Select(SDNode *Node);
bool TryFoldLoad(SDValue P, SDValue N,
bool TryFoldLoad(SDNode *P, SDValue N,
SDValue &Base, SDValue &Disp, SDValue &Index);
bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
@ -367,12 +367,12 @@ void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
/// Returns true if the address can be represented by a base register plus
/// an unsigned 12-bit displacement [r+imm].
bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDValue Op, SDValue& Addr,
bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDNode *Op, SDValue& Addr,
SDValue &Base, SDValue &Disp) {
return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true);
}
bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr,
bool SystemZDAGToDAGISel::SelectAddrRI12(SDNode *Op, SDValue& Addr,
SDValue &Base, SDValue &Disp,
bool is12BitOnly) {
SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
@ -422,7 +422,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr,
/// Returns true if the address can be represented by a base register plus
/// a signed 20-bit displacement [r+imm].
bool SystemZDAGToDAGISel::SelectAddrRI(SDValue Op, SDValue& Addr,
bool SystemZDAGToDAGISel::SelectAddrRI(SDNode *Op, SDValue& Addr,
SDValue &Base, SDValue &Disp) {
SystemZRRIAddressMode AM(/*isRI*/true);
bool Done = false;
@ -465,7 +465,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI(SDValue Op, SDValue& Addr,
/// Returns true if the address can be represented by a base register plus
/// index register plus an unsigned 12-bit displacement [base + idx + imm].
bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr,
bool SystemZDAGToDAGISel::SelectAddrRRI12(SDNode *Op, SDValue Addr,
SDValue &Base, SDValue &Disp, SDValue &Index) {
SystemZRRIAddressMode AM20, AM12;
bool Done = false;
@ -514,7 +514,7 @@ bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr,
/// Returns true if the address can be represented by a base register plus
/// index register plus a signed 20-bit displacement [base + idx + imm].
bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Op, SDValue Addr,
bool SystemZDAGToDAGISel::SelectAddrRRI20(SDNode *Op, SDValue Addr,
SDValue &Base, SDValue &Disp, SDValue &Index) {
SystemZRRIAddressMode AM;
bool Done = false;
@ -558,7 +558,7 @@ bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Op, SDValue Addr,
/// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing
/// mode it matches can be cost effectively emitted as an LA/LAY instruction.
bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Op, SDValue Addr,
bool SystemZDAGToDAGISel::SelectLAAddr(SDNode *Op, SDValue Addr,
SDValue &Base, SDValue &Disp, SDValue &Index) {
SystemZRRIAddressMode AM;
@ -591,11 +591,11 @@ bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Op, SDValue Addr,
return false;
}
bool SystemZDAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
bool SystemZDAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
SDValue &Base, SDValue &Disp, SDValue &Index) {
if (ISD::isNON_EXTLoad(N.getNode()) &&
N.hasOneUse() &&
IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
IsLegalAndProfitableToFold(N.getNode(), P, P))
return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index);
return false;
}
@ -612,10 +612,9 @@ void SystemZDAGToDAGISel::InstructionSelect() {
CurDAG->RemoveDeadNodes();
}
SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
SDNode *Node = Op.getNode();
SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
EVT NVT = Node->getValueType(0);
DebugLoc dl = Op.getDebugLoc();
DebugLoc dl = Node->getDebugLoc();
unsigned Opcode = Node->getOpcode();
// Dump information about the Node being selected
@ -656,7 +655,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
}
SDValue Tmp0, Tmp1, Tmp2;
bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2);
// Prepare the dividend
SDNode *Dividend;
@ -686,7 +685,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
}
// Copy the division (odd subreg) result, if it is needed.
if (!Op.getValue(0).use_empty()) {
if (!SDValue(Node, 0).use_empty()) {
unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
SDNode *Div = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG,
dl, NVT,
@ -694,14 +693,14 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
CurDAG->getTargetConstant(SubRegIdx,
MVT::i32));
ReplaceUses(Op.getValue(0), SDValue(Div, 0));
ReplaceUses(SDValue(Node, 0), SDValue(Div, 0));
DEBUG(errs().indent(Indent-2) << "=> ";
Result->dump(CurDAG);
errs() << "\n");
}
// Copy the remainder (even subreg) result, if it is needed.
if (!Op.getValue(1).use_empty()) {
if (!SDValue(Node, 1).use_empty()) {
unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
SDNode *Rem = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG,
dl, NVT,
@ -709,7 +708,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
CurDAG->getTargetConstant(SubRegIdx,
MVT::i32));
ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0));
DEBUG(errs().indent(Indent-2) << "=> ";
Result->dump(CurDAG);
errs() << "\n");
@ -744,7 +743,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
}
SDValue Tmp0, Tmp1, Tmp2;
bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2);
// Prepare the dividend
SDNode *Dividend = N0.getNode();
@ -776,28 +775,28 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
}
// Copy the division (odd subreg) result, if it is needed.
if (!Op.getValue(0).use_empty()) {
if (!SDValue(Node, 0).use_empty()) {
unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
SDNode *Div = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG,
dl, NVT,
SDValue(Result, 0),
CurDAG->getTargetConstant(SubRegIdx,
MVT::i32));
ReplaceUses(Op.getValue(0), SDValue(Div, 0));
ReplaceUses(SDValue(Node, 0), SDValue(Div, 0));
DEBUG(errs().indent(Indent-2) << "=> ";
Result->dump(CurDAG);
errs() << "\n");
}
// Copy the remainder (even subreg) result, if it is needed.
if (!Op.getValue(1).use_empty()) {
if (!SDValue(Node, 1).use_empty()) {
unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
SDNode *Rem = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG,
dl, NVT,
SDValue(Result, 0),
CurDAG->getTargetConstant(SubRegIdx,
MVT::i32));
ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0));
DEBUG(errs().indent(Indent-2) << "=> ";
Result->dump(CurDAG);
errs() << "\n");
@ -812,11 +811,11 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
}
// Select the default instruction
SDNode *ResNode = SelectCode(Op);
SDNode *ResNode = SelectCode(Node);
DEBUG(errs().indent(Indent-2) << "=> ";
if (ResNode == NULL || ResNode == Op.getNode())
Op.getNode()->dump(CurDAG);
if (ResNode == NULL || ResNode == Node)
Node->dump(CurDAG);
else
ResNode->dump(CurDAG);
errs() << "\n";

67
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -190,7 +190,7 @@ namespace {
#include "X86GenDAGISel.inc"
private:
SDNode *Select(SDValue N);
SDNode *Select(SDNode *N);
SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
@ -201,19 +201,19 @@ namespace {
bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
unsigned Depth);
bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Scale, SDValue &Index, SDValue &Disp,
SDValue &Segment);
bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
bool SelectLEAAddr(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Scale, SDValue &Index, SDValue &Disp);
bool SelectTLSADDRAddr(SDValue Op, SDValue N, SDValue &Base,
bool SelectTLSADDRAddr(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Scale, SDValue &Index, SDValue &Disp);
bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
bool SelectScalarSSELoad(SDNode *Op, SDValue Pred,
SDValue N, SDValue &Base, SDValue &Scale,
SDValue &Index, SDValue &Disp,
SDValue &Segment,
SDValue &InChain, SDValue &OutChain);
bool TryFoldLoad(SDValue P, SDValue N,
bool TryFoldLoad(SDNode *P, SDValue N,
SDValue &Base, SDValue &Scale,
SDValue &Index, SDValue &Disp,
SDValue &Segment);
@ -1273,7 +1273,7 @@ bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
/// SelectAddr - returns true if it is able pattern match an addressing mode.
/// It returns the operands which make up the maximal addressing mode it can
/// match by reference.
bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
bool X86DAGToDAGISel::SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Scale, SDValue &Index,
SDValue &Disp, SDValue &Segment) {
X86ISelAddressMode AM;
@ -1296,7 +1296,7 @@ bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
/// match a load whose top elements are either undef or zeros. The load flavor
/// is derived from the type of N, which is either v4f32 or v2f64.
bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Op, SDValue Pred,
SDValue N, SDValue &Base,
SDValue &Scale, SDValue &Index,
SDValue &Disp, SDValue &Segment,
@ -1307,7 +1307,7 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
if (ISD::isNON_EXTLoad(InChain.getNode()) &&
InChain.getValue(0).hasOneUse() &&
N.hasOneUse() &&
IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op.getNode())) {
IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op)) {
LoadSDNode *LD = cast<LoadSDNode>(InChain);
if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
return false;
@ -1338,7 +1338,7 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
/// mode it matches can be cost effectively emitted as an LEA instruction.
bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N,
bool X86DAGToDAGISel::SelectLEAAddr(SDNode *Op, SDValue N,
SDValue &Base, SDValue &Scale,
SDValue &Index, SDValue &Disp) {
X86ISelAddressMode AM;
@ -1400,10 +1400,10 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N,
}
/// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue Op, SDValue N, SDValue &Base,
bool X86DAGToDAGISel::SelectTLSADDRAddr(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Scale, SDValue &Index,
SDValue &Disp) {
assert(Op.getOpcode() == X86ISD::TLSADDR);
assert(Op->getOpcode() == X86ISD::TLSADDR);
assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
@ -1426,13 +1426,13 @@ bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue Op, SDValue N, SDValue &Base,
}
bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
SDValue &Base, SDValue &Scale,
SDValue &Index, SDValue &Disp,
SDValue &Segment) {
if (ISD::isNON_EXTLoad(N.getNode()) &&
N.hasOneUse() &&
IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
IsLegalAndProfitableToFold(N.getNode(), P, P))
return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);
return false;
}
@ -1459,7 +1459,7 @@ SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
SDValue In2L = Node->getOperand(2);
SDValue In2H = Node->getOperand(3);
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
if (!SelectAddr(In1.getNode(), In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
return NULL;
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
@ -1485,7 +1485,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
SDValue Ptr = Node->getOperand(1);
SDValue Val = Node->getOperand(2);
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
if (!SelectAddr(Ptr, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
if (!SelectAddr(Ptr.getNode(), Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
return 0;
bool isInc = false, isDec = false, isSub = false, isCN = false;
@ -1683,8 +1683,7 @@ static bool HasNoSignedComparisonUses(SDNode *N) {
return true;
}
SDNode *X86DAGToDAGISel::Select(SDValue N) {
SDNode *Node = N.getNode();
SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
EVT NVT = Node->getValueType(0);
unsigned Opc, MOpc;
unsigned Opcode = Node->getOpcode();
@ -1772,10 +1771,10 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
}
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
// Multiply is commmutative.
if (!foldedLoad) {
foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
if (foldedLoad)
std::swap(N0, N1);
}
@ -1798,11 +1797,11 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
}
// Copy the low half of the result, if it is needed.
if (!N.getValue(0).use_empty()) {
if (!SDValue(Node, 0).use_empty()) {
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
LoReg, NVT, InFlag);
InFlag = Result.getValue(2);
ReplaceUses(N.getValue(0), Result);
ReplaceUses(SDValue(Node, 0), Result);
#ifndef NDEBUG
DEBUG({
errs() << std::string(Indent-2, ' ') << "=> ";
@ -1812,7 +1811,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
#endif
}
// Copy the high half of the result, if it is needed.
if (!N.getValue(1).use_empty()) {
if (!SDValue(Node, 1).use_empty()) {
SDValue Result;
if (HiReg == X86::AH && Subtarget->is64Bit()) {
// Prevent use of AH in a REX instruction by referencing AX instead.
@ -1831,7 +1830,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
HiReg, NVT, InFlag);
InFlag = Result.getValue(2);
}
ReplaceUses(N.getValue(1), Result);
ReplaceUses(SDValue(Node, 1), Result);
#ifndef NDEBUG
DEBUG({
errs() << std::string(Indent-2, ' ') << "=> ";
@ -1900,7 +1899,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
}
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
bool signBitIsZero = CurDAG->SignBitIsZero(N0);
SDValue InFlag;
@ -1908,7 +1907,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
// Special case for div8, just use a move with zero extension to AX to
// clear the upper 8 bits (AH).
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
Move =
SDValue(CurDAG->getMachineNode(X86::MOVZX16rm8, dl, MVT::i16,
@ -1971,11 +1970,11 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
}
// Copy the division (low) result, if it is needed.
if (!N.getValue(0).use_empty()) {
if (!SDValue(Node, 0).use_empty()) {
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
LoReg, NVT, InFlag);
InFlag = Result.getValue(2);
ReplaceUses(N.getValue(0), Result);
ReplaceUses(SDValue(Node, 0), Result);
#ifndef NDEBUG
DEBUG({
errs() << std::string(Indent-2, ' ') << "=> ";
@ -1985,7 +1984,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
#endif
}
// Copy the remainder (high) result, if it is needed.
if (!N.getValue(1).use_empty()) {
if (!SDValue(Node, 1).use_empty()) {
SDValue Result;
if (HiReg == X86::AH && Subtarget->is64Bit()) {
// Prevent use of AH in a REX instruction by referencing AX instead.
@ -2005,7 +2004,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
HiReg, NVT, InFlag);
InFlag = Result.getValue(2);
}
ReplaceUses(N.getValue(1), Result);
ReplaceUses(SDValue(Node, 1), Result);
#ifndef NDEBUG
DEBUG({
errs() << std::string(Indent-2, ' ') << "=> ";
@ -2129,13 +2128,13 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
}
}
SDNode *ResNode = SelectCode(N);
SDNode *ResNode = SelectCode(Node);
#ifndef NDEBUG
DEBUG({
errs() << std::string(Indent-2, ' ') << "=> ";
if (ResNode == NULL || ResNode == N.getNode())
N.getNode()->dump(CurDAG);
if (ResNode == NULL || ResNode == Node)
Node->dump(CurDAG);
else
ResNode->dump(CurDAG);
errs() << '\n';
@ -2155,7 +2154,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
case 'v': // not offsetable ??
default: return true;
case 'm': // memory
if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3, Op4))
if (!SelectAddr(Op.getNode(), Op, Op0, Op1, Op2, Op3, Op4))
return true;
break;
}

31
lib/Target/XCore/XCoreISelDAGToDAG.cpp
View File

@ -49,7 +49,7 @@ namespace {
Lowering(*TM.getTargetLowering()),
Subtarget(*TM.getSubtargetImpl()) { }
SDNode *Select(SDValue Op);
SDNode *Select(SDNode *N);
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
@ -58,11 +58,11 @@ namespace {
}
// Complex Pattern Selectors.
bool SelectADDRspii(SDValue Op, SDValue Addr, SDValue &Base,
bool SelectADDRspii(SDNode *Op, SDValue Addr, SDValue &Base,
SDValue &Offset);
bool SelectADDRdpii(SDValue Op, SDValue Addr, SDValue &Base,
bool SelectADDRdpii(SDNode *Op, SDValue Addr, SDValue &Base,
SDValue &Offset);
bool SelectADDRcpii(SDValue Op, SDValue Addr, SDValue &Base,
bool SelectADDRcpii(SDNode *Op, SDValue Addr, SDValue &Base,
SDValue &Offset);
virtual void InstructionSelect();
@ -83,7 +83,7 @@ FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM) {
return new XCoreDAGToDAGISel(TM);
}
bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Op, SDValue Addr,
bool XCoreDAGToDAGISel::SelectADDRspii(SDNode *Op, SDValue Addr,
SDValue &Base, SDValue &Offset) {
FrameIndexSDNode *FIN = 0;
if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
@ -105,7 +105,7 @@ bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Op, SDValue Addr,
return false;
}
bool XCoreDAGToDAGISel::SelectADDRdpii(SDValue Op, SDValue Addr,
bool XCoreDAGToDAGISel::SelectADDRdpii(SDNode *Op, SDValue Addr,
SDValue &Base, SDValue &Offset) {
if (Addr.getOpcode() == XCoreISD::DPRelativeWrapper) {
Base = Addr.getOperand(0);
@ -126,7 +126,7 @@ bool XCoreDAGToDAGISel::SelectADDRdpii(SDValue Op, SDValue Addr,
return false;
}
bool XCoreDAGToDAGISel::SelectADDRcpii(SDValue Op, SDValue Addr,
bool XCoreDAGToDAGISel::SelectADDRcpii(SDNode *Op, SDValue Addr,
SDValue &Base, SDValue &Offset) {
if (Addr.getOpcode() == XCoreISD::CPRelativeWrapper) {
Base = Addr.getOperand(0);
@ -156,8 +156,7 @@ void XCoreDAGToDAGISel::InstructionSelect() {
CurDAG->RemoveDeadNodes();
}
SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.getNode();
SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
EVT NVT = N->getValueType(0);
if (NVT == MVT::i32) {
@ -185,7 +184,7 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
// FIXME fold addition into the macc instruction
SDValue Zero(CurDAG->getMachineNode(XCore::LDC_ru6, dl, MVT::i32,
CurDAG->getTargetConstant(0, MVT::i32)), 0);
SDValue Ops[] = { Zero, Zero, Op.getOperand(0), Op.getOperand(1) };
SDValue Ops[] = { Zero, Zero, N->getOperand(0), N->getOperand(1) };
SDNode *ResNode = CurDAG->getMachineNode(XCore::MACCS_l4r, dl,
MVT::i32, MVT::i32, Ops, 4);
ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1));
@ -196,7 +195,7 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
// FIXME fold addition into the macc / lmul instruction
SDValue Zero(CurDAG->getMachineNode(XCore::LDC_ru6, dl, MVT::i32,
CurDAG->getTargetConstant(0, MVT::i32)), 0);
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
Zero, Zero };
SDNode *ResNode = CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32,
MVT::i32, Ops, 4);
@ -205,19 +204,19 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
return NULL;
}
case XCoreISD::LADD: {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
Op.getOperand(2) };
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
N->getOperand(2) };
return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
Ops, 3);
}
case XCoreISD::LSUB: {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
Op.getOperand(2) };
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
N->getOperand(2) };
return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
Ops, 3);
}
// Other cases are autogenerated.
}
}
return SelectCode(Op);
return SelectCode(N);
}

177
utils/TableGen/DAGISelEmitter.cpp
View File

@ -30,6 +30,22 @@ GenDebug("gen-debug", cl::desc("Generate debug code"), cl::init(false));
// DAGISelEmitter Helper methods
//
/// getNodeName - The top level Select_* functions have an "SDNode* N"
/// argument. When expanding the pattern-matching code, the intermediate
/// variables have type SDValue. This function provides a uniform way to
/// reference the underlying "SDNode *" for both cases.
static std::string getNodeName(const std::string &S) {
if (S == "N") return S;
return S + ".getNode()";
}
/// getNodeValue - Similar to getNodeName, except it provides a uniform
/// way to access the SDValue for both cases.
static std::string getValueName(const std::string &S) {
if (S == "N") return "SDValue(N, 0)";
return S;
}
/// NodeIsComplexPattern - return true if N is a leaf node and a subclass of
/// ComplexPattern.
static bool NodeIsComplexPattern(TreePatternNode *N) {
@ -452,7 +468,7 @@ public:
// Save loads/stores matched by a pattern.
if (!N->isLeaf() && N->getName().empty()) {
if (NodeHasProperty(N, SDNPMemOperand, CGP))
LSI.push_back(RootName);
LSI.push_back(getNodeName(RootName));
}
bool isRoot = (P == NULL);
@ -469,7 +485,7 @@ public:
if (N->isLeaf()) {
if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
emitCheck("cast<ConstantSDNode>(" + RootName +
emitCheck("cast<ConstantSDNode>(" + getNodeName(RootName) +
")->getSExtValue() == INT64_C(" +
itostr(II->getValue()) + ")");
return;
@ -509,7 +525,7 @@ public:
OpNo = 1;
if (!isRoot) {
// Multiple uses of actual result?
emitCheck(RootName + ".hasOneUse()");
emitCheck(getValueName(RootName) + ".hasOneUse()");
EmittedUseCheck = true;
if (NodeHasChain) {
// If the immediate use can somehow reach this node through another
@ -540,23 +556,25 @@ public:
if (NeedCheck) {
std::string ParentName(RootName.begin(), RootName.end()-1);
emitCheck("IsLegalAndProfitableToFold(" + RootName +
".getNode(), " + ParentName + ".getNode(), N.getNode())");
emitCheck("IsLegalAndProfitableToFold(" + getNodeName(RootName) +
", " + getNodeName(ParentName) + ", N)");
}
}
}
if (NodeHasChain) {
if (FoundChain) {
emitCheck("(" + ChainName + ".getNode() == " + RootName + ".getNode() || "
emitCheck("(" + ChainName + ".getNode() == " +
getNodeName(RootName) + " || "
"IsChainCompatible(" + ChainName + ".getNode(), " +
RootName + ".getNode()))");
OrigChains.push_back(std::make_pair(ChainName, RootName));
getNodeName(RootName) + "))");
OrigChains.push_back(std::make_pair(ChainName,
getValueName(RootName)));
} else
FoundChain = true;
ChainName = "Chain" + ChainSuffix;
emitInit("SDValue " + ChainName + " = " + RootName +
".getOperand(0);");
emitInit("SDValue " + ChainName + " = " + getNodeName(RootName) +
"->getOperand(0);");
}
}
@ -571,13 +589,13 @@ public:
PatternHasProperty(N, SDNPOutFlag, CGP))) {
if (!EmittedUseCheck) {
// Multiple uses of actual result?
emitCheck(RootName + ".hasOneUse()");
emitCheck(getValueName(RootName) + ".hasOneUse()");
}
}
// If there are node predicates for this, emit the calls.
for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i)
emitCheck(N->getPredicateFns()[i] + "(" + RootName + ".getNode())");
emitCheck(N->getPredicateFns()[i] + "(" + getNodeName(RootName) + ")");
// If this is an 'and R, 1234' where the operation is AND/OR and the RHS is
// a constant without a predicate fn that has more that one bit set, handle
@ -597,17 +615,19 @@ public:
if (IntInit *II = dynamic_cast<IntInit*>(N->getChild(1)->getLeafValue())) {
if (!isPowerOf2_32(II->getValue())) { // Don't bother with single bits.
emitInit("SDValue " + RootName + "0" + " = " +
RootName + ".getOperand(" + utostr(0) + ");");
getNodeName(RootName) + "->getOperand(" + utostr(0) + ");");
emitInit("SDValue " + RootName + "1" + " = " +
RootName + ".getOperand(" + utostr(1) + ");");
getNodeName(RootName) + "->getOperand(" + utostr(1) + ");");
unsigned NTmp = TmpNo++;
emitCode("ConstantSDNode *Tmp" + utostr(NTmp) +
" = dyn_cast<ConstantSDNode>(" + RootName + "1);");
" = dyn_cast<ConstantSDNode>(" +
getNodeName(RootName + "1") + ");");
emitCheck("Tmp" + utostr(NTmp));
const char *MaskPredicate = N->getOperator()->getName() == "or"
? "CheckOrMask(" : "CheckAndMask(";
emitCheck(MaskPredicate + RootName + "0, Tmp" + utostr(NTmp) +
emitCheck(MaskPredicate + getValueName(RootName + "0") +
", Tmp" + utostr(NTmp) +
", INT64_C(" + itostr(II->getValue()) + "))");
EmitChildMatchCode(N->getChild(0), N, RootName + utostr(0),
@ -618,8 +638,8 @@ public:
}
for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
emitInit("SDValue " + RootName + utostr(OpNo) + " = " +
RootName + ".getOperand(" +utostr(OpNo) + ");");
emitInit("SDValue " + getValueName(RootName + utostr(OpNo)) + " = " +
getNodeName(RootName) + "->getOperand(" + utostr(OpNo) + ");");
EmitChildMatchCode(N->getChild(i), N, RootName + utostr(OpNo),
ChainSuffix + utostr(OpNo), FoundChain);
@ -641,7 +661,9 @@ public:
emitCode("SDValue Chain" + ChainSuffix + ";");
}
std::string Code = Fn + "(" + RootName + ", " + RootName;
std::string Code = Fn + "(" +
getNodeName(RootName) + ", " +
getValueName(RootName);
for (unsigned i = 0; i < NumOps; i++)
Code += ", CPTmp" + RootName + "_" + utostr(i);
if (CP->hasProperty(SDNPHasChain)) {
@ -658,18 +680,19 @@ public:
if (!Child->isLeaf()) {
// If it's not a leaf, recursively match.
const SDNodeInfo &CInfo = CGP.getSDNodeInfo(Child->getOperator());
emitCheck(RootName + ".getOpcode() == " +
emitCheck(getNodeName(RootName) + "->getOpcode() == " +
CInfo.getEnumName());
EmitMatchCode(Child, Parent, RootName, ChainSuffix, FoundChain);
bool HasChain = false;
if (NodeHasProperty(Child, SDNPHasChain, CGP)) {
HasChain = true;
FoldedChains.push_back(std::make_pair(RootName, CInfo.getNumResults()));
FoldedChains.push_back(std::make_pair(getValueName(RootName),
CInfo.getNumResults()));
}
if (NodeHasProperty(Child, SDNPOutFlag, CGP)) {
assert(FoldedFlag.first == "" && FoldedFlag.second == 0 &&
"Pattern folded multiple nodes which produce flags?");
FoldedFlag = std::make_pair(RootName,
FoldedFlag = std::make_pair(getValueName(RootName),
CInfo.getNumResults() + (unsigned)HasChain);
}
} else {
@ -678,14 +701,14 @@ public:
if (!Child->getName().empty()) {
std::string &VarMapEntry = VariableMap[Child->getName()];
if (VarMapEntry.empty()) {
VarMapEntry = RootName;
VarMapEntry = getValueName(RootName);
} else {
// If we get here, this is a second reference to a specific name.
// Since we already have checked that the first reference is valid,
// we don't have to recursively match it, just check that it's the
// same as the previously named thing.
emitCheck(VarMapEntry + " == " + RootName);
Duplicates.insert(RootName);
emitCheck(VarMapEntry + " == " + getValueName(RootName));
Duplicates.insert(getValueName(RootName));
return;
}
}
@ -721,9 +744,9 @@ public:
std::string Code = Fn + "(N, ";
if (CP->hasProperty(SDNPHasChain)) {
std::string ParentName(RootName.begin(), RootName.end()-1);
Code += ParentName + ", ";
Code += getValueName(ParentName) + ", ";
}
Code += RootName;
Code += getValueName(RootName);
for (unsigned i = 0; i < NumOps; i++)
Code += ", CPTmp" + RootName + "_" + utostr(i);
if (CP->hasProperty(SDNPHasChain))
@ -733,11 +756,11 @@ public:
// Place holder for SRCVALUE nodes. Nothing to do here.
} else if (LeafRec->isSubClassOf("ValueType")) {
// Make sure this is the specified value type.
emitCheck("cast<VTSDNode>(" + RootName +
emitCheck("cast<VTSDNode>(" + getNodeName(RootName) +
")->getVT() == MVT::" + LeafRec->getName());
} else if (LeafRec->isSubClassOf("CondCode")) {
// Make sure this is the specified cond code.
emitCheck("cast<CondCodeSDNode>(" + RootName +
emitCheck("cast<CondCodeSDNode>(" + getNodeName(RootName) +
")->get() == ISD::" + LeafRec->getName());
} else {
#ifndef NDEBUG
@ -749,14 +772,14 @@ public:
// If there are node predicates for this, emit the calls.
for (unsigned i = 0, e = Child->getPredicateFns().size(); i != e; ++i)
emitCheck(Child->getPredicateFns()[i] + "(" + RootName +
".getNode())");
emitCheck(Child->getPredicateFns()[i] + "(" + getNodeName(RootName) +
")");
} else if (IntInit *II =
dynamic_cast<IntInit*>(Child->getLeafValue())) {
unsigned NTmp = TmpNo++;
emitCode("ConstantSDNode *Tmp"+ utostr(NTmp) +
" = dyn_cast<ConstantSDNode>("+
RootName + ");");
getNodeName(RootName) + ");");
emitCheck("Tmp" + utostr(NTmp));
unsigned CTmp = TmpNo++;
emitCode("int64_t CN"+ utostr(CTmp) +
@ -792,7 +815,7 @@ public:
}
if (Val[0] == 'T' && Val[1] == 'm' && Val[2] == 'p') {
// Already selected this operand, just return the tmpval.
NodeOps.push_back(Val);
NodeOps.push_back(getValueName(Val));
return NodeOps;
}
@ -821,7 +844,7 @@ public:
// value if used multiple times by this pattern result.
Val = TmpVar;
ModifiedVal = true;
NodeOps.push_back(Val);
NodeOps.push_back(getValueName(Val));
} else if (!N->isLeaf() && N->getOperator()->getName() == "fpimm") {
assert(N->getExtTypes().size() == 1 && "Multiple types not handled!");
std::string TmpVar = "Tmp" + utostr(ResNo);
@ -833,7 +856,7 @@ public:
// value if used multiple times by this pattern result.
Val = TmpVar;
ModifiedVal = true;
NodeOps.push_back(Val);
NodeOps.push_back(getValueName(Val));
} else if (!N->isLeaf() && N->getOperator()->getName() == "texternalsym"){
Record *Op = OperatorMap[N->getName()];
// Transform ExternalSymbol to TargetExternalSymbol
@ -848,7 +871,7 @@ public:
Val = TmpVar;
ModifiedVal = true;
}
NodeOps.push_back(Val);
NodeOps.push_back(getValueName(Val));
} else if (!N->isLeaf() && (N->getOperator()->getName() == "tglobaladdr"
|| N->getOperator()->getName() == "tglobaltlsaddr")) {
Record *Op = OperatorMap[N->getName()];
@ -865,27 +888,27 @@ public:
Val = TmpVar;
ModifiedVal = true;
}
NodeOps.push_back(Val);
NodeOps.push_back(getValueName(Val));
} else if (!N->isLeaf()
&& (N->getOperator()->getName() == "texternalsym"
|| N->getOperator()->getName() == "tconstpool")) {
// Do not rewrite the variable name, since we don't generate a new
// temporary.
NodeOps.push_back(Val);
NodeOps.push_back(getValueName(Val));
} else if (N->isLeaf() && (CP = NodeGetComplexPattern(N, CGP))) {
for (unsigned i = 0; i < CP->getNumOperands(); ++i) {
NodeOps.push_back("CPTmp" + Val + "_" + utostr(i));
NodeOps.push_back(getValueName("CPTmp" + Val + "_" + utostr(i)));
}
} else {
// This node, probably wrapped in a SDNodeXForm, behaves like a leaf
// node even if it isn't one. Don't select it.
if (!LikeLeaf) {
if (isRoot && N->isLeaf()) {
emitCode("ReplaceUses(N, " + Val + ");");
emitCode("ReplaceUses(SDValue(N, 0), " + Val + ");");
emitCode("return NULL;");
}
}
NodeOps.push_back(Val);
NodeOps.push_back(getValueName(Val));
}
if (ModifiedVal) {
@ -901,13 +924,13 @@ public:
emitCode("SDValue Tmp" + utostr(ResNo) + " = CurDAG->getRegister(" +
getQualifiedName(DI->getDef()) + ", " +
getEnumName(N->getTypeNum(0)) + ");");
NodeOps.push_back("Tmp" + utostr(ResNo));
NodeOps.push_back(getValueName("Tmp" + utostr(ResNo)));
return NodeOps;
} else if (DI->getDef()->getName() == "zero_reg") {
emitCode("SDValue Tmp" + utostr(ResNo) +
" = CurDAG->getRegister(0, " +
getEnumName(N->getTypeNum(0)) + ");");
NodeOps.push_back("Tmp" + utostr(ResNo));
NodeOps.push_back(getValueName("Tmp" + utostr(ResNo)));
return NodeOps;
} else if (DI->getDef()->isSubClassOf("RegisterClass")) {
// Handle a reference to a register class. This is used
@ -916,7 +939,7 @@ public:
" = CurDAG->getTargetConstant(" +
getQualifiedName(DI->getDef()) + "RegClassID, " +
"MVT::i32);");
NodeOps.push_back("Tmp" + utostr(ResNo));
NodeOps.push_back(getValueName("Tmp" + utostr(ResNo)));
return NodeOps;
}
} else if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
@ -926,7 +949,7 @@ public:
" = CurDAG->getTargetConstant(0x" +
utohexstr((uint64_t) II->getValue()) +
"ULL, " + getEnumName(N->getTypeNum(0)) + ");");
NodeOps.push_back("Tmp" + utostr(ResNo));
NodeOps.push_back(getValueName("Tmp" + utostr(ResNo)));
return NodeOps;
}
@ -973,7 +996,8 @@ public:
if (NodeHasOptInFlag) {
emitCode("bool HasInFlag = "
"(N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);");
"(N->getOperand(N->getNumOperands()-1).getValueType() == "
"MVT::Flag);");
}
if (IsVariadic)
emitCode("SmallVector<SDValue, 8> Ops" + utostr(OpcNo) + ";");
@ -1001,7 +1025,7 @@ public:
}
emitCode("InChains.push_back(" + ChainName + ");");
emitCode(ChainName + " = CurDAG->getNode(ISD::TokenFactor, "
"N.getDebugLoc(), MVT::Other, "
"N->getDebugLoc(), MVT::Other, "
"&InChains[0], InChains.size());");
if (GenDebug) {
emitCode("CurDAG->setSubgraphColor(" + ChainName +".getNode(), \"yellow\");");
@ -1056,7 +1080,7 @@ public:
}
if (NodeHasOptInFlag) {
emitCode("if (HasInFlag) {");
emitCode(" InFlag = N.getOperand(N.getNumOperands()-1);");
emitCode(" InFlag = N->getOperand(N->getNumOperands()-1);");
emitCode("}");
}
}
@ -1084,7 +1108,7 @@ public:
if (!isRoot || (InputHasChain && !NodeHasChain))
// For call to "getMachineNode()".
Code += ", N.getDebugLoc()";
Code += ", N->getDebugLoc()";
emitOpcode(II.Namespace + "::" + II.TheDef->getName());
@ -1123,9 +1147,9 @@ public:
EndAdjust = "-(HasInFlag?1:0)"; // May have a flag.
emitCode("for (unsigned i = NumInputRootOps + " + utostr(NodeHasChain) +
", e = N.getNumOperands()" + EndAdjust + "; i != e; ++i) {");
", e = N->getNumOperands()" + EndAdjust + "; i != e; ++i) {");
emitCode(" Ops" + utostr(OpsNo) + ".push_back(N.getOperand(i));");
emitCode(" Ops" + utostr(OpsNo) + ".push_back(N->getOperand(i));");
emitCode("}");
}
@ -1221,7 +1245,7 @@ public:
ReplaceTos.push_back("InFlag");
} else {
assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP));
ReplaceFroms.push_back("SDValue(N.getNode(), " +
ReplaceFroms.push_back("SDValue(N, " +
utostr(NumPatResults + (unsigned)InputHasChain)
+ ")");
ReplaceTos.push_back("InFlag");
@ -1229,7 +1253,7 @@ public:
}
if (!ReplaceFroms.empty() && InputHasChain) {
ReplaceFroms.push_back("SDValue(N.getNode(), " +
ReplaceFroms.push_back("SDValue(N, " +
utostr(NumPatResults) + ")");
ReplaceTos.push_back("SDValue(" + ChainName + ".getNode(), " +
ChainName + ".getResNo()" + ")");
@ -1242,7 +1266,7 @@ public:
} else if (InputHasChain && !NodeHasChain) {
// One of the inner node produces a chain.
assert(!NodeHasOutFlag && "Node has flag but not chain!");
ReplaceFroms.push_back("SDValue(N.getNode(), " +
ReplaceFroms.push_back("SDValue(N, " +
utostr(NumPatResults) + ")");
ReplaceTos.push_back(ChainName);
}
@ -1288,7 +1312,7 @@ public:
if (!isRoot || (InputHasChain && !NodeHasChain)) {
Code = "CurDAG->getMachineNode(" + Code;
} else {
Code = "CurDAG->SelectNodeTo(N.getNode(), " + Code;
Code = "CurDAG->SelectNodeTo(N, " + Code;
}
if (isRoot) {
if (After.empty())
@ -1391,10 +1415,12 @@ private:
MVT::SimpleValueType RVT = getRegisterValueType(RR, T);
if (RVT == MVT::Flag) {
if (!InFlagDecled) {
emitCode("SDValue InFlag = " + RootName + utostr(OpNo) + ";");
emitCode("SDValue InFlag = " +
getValueName(RootName + utostr(OpNo)) + ";");
InFlagDecled = true;
} else
emitCode("InFlag = " + RootName + utostr(OpNo) + ";");
emitCode("InFlag = " +
getValueName(RootName + utostr(OpNo)) + ";");
} else {
if (!ChainEmitted) {
emitCode("SDValue Chain = CurDAG->getEntryNode();");
@ -1407,9 +1433,10 @@ private:
}
std::string Decl = (!ResNodeDecled) ? "SDNode *" : "";
emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + ChainName +
", " + RootName + ".getDebugLoc()" +
", " + getNodeName(RootName) + "->getDebugLoc()" +
", " + getQualifiedName(RR) +
", " + RootName + utostr(OpNo) + ", InFlag).getNode();");
", " + getValueName(RootName + utostr(OpNo)) +
", InFlag).getNode();");
ResNodeDecled = true;
emitCode(ChainName + " = SDValue(ResNode, 0);");
emitCode("InFlag = SDValue(ResNode, 1);");
@ -1421,12 +1448,12 @@ private:
if (HasInFlag) {
if (!InFlagDecled) {
emitCode("SDValue InFlag = " + RootName +
".getOperand(" + utostr(OpNo) + ");");
emitCode("SDValue InFlag = " + getNodeName(RootName) +
"->getOperand(" + utostr(OpNo) + ");");
InFlagDecled = true;
} else
emitCode("InFlag = " + RootName +
".getOperand(" + utostr(OpNo) + ");");
emitCode("InFlag = " + getNodeName(RootName) +
"->getOperand(" + utostr(OpNo) + ");");
}
}
};
@ -1752,7 +1779,7 @@ void DAGISelEmitter::EmitInstructionSelector(raw_ostream &OS) {
AddedInits.push_back(GeneratedCode[j].second);
}
std::string CalleeCode = "(const SDValue &N";
std::string CalleeCode = "(SDNode *N";
std::string CallerCode = "(N";
for (unsigned j = 0, e = TargetOpcodes.size(); j != e; ++j) {
CalleeCode += ", unsigned Opc" + utostr(j);
@ -1805,7 +1832,7 @@ void DAGISelEmitter::EmitInstructionSelector(raw_ostream &OS) {
// Replace the emission code within selection routines with calls to the
// emission functions.
if (GenDebug) {
GeneratedCode.push_back(std::make_pair(0, "CurDAG->setSubgraphColor(N.getNode(), \"red\");"));
GeneratedCode.push_back(std::make_pair(0, "CurDAG->setSubgraphColor(N, \"red\");"));
}
CallerCode = "SDNode *Result = Emit_" + utostr(EmitFuncNum) + CallerCode;
GeneratedCode.push_back(std::make_pair(3, CallerCode));
@ -1814,7 +1841,7 @@ void DAGISelEmitter::EmitInstructionSelector(raw_ostream &OS) {
GeneratedCode.push_back(std::make_pair(0, " CurDAG->setSubgraphColor(Result, \"yellow\");"));
GeneratedCode.push_back(std::make_pair(0, " CurDAG->setSubgraphColor(Result, \"black\");"));
GeneratedCode.push_back(std::make_pair(0, "}"));
//GeneratedCode.push_back(std::make_pair(0, "CurDAG->setSubgraphColor(N.getNode(), \"black\");"));
//GeneratedCode.push_back(std::make_pair(0, "CurDAG->setSubgraphColor(N, \"black\");"));
}
GeneratedCode.push_back(std::make_pair(0, "return Result;"));
}
@ -1883,7 +1910,7 @@ void DAGISelEmitter::EmitInstructionSelector(raw_ostream &OS) {
std::reverse(CodeForPatterns.begin(), CodeForPatterns.end());
OS << "SDNode *Select_" << getLegalCName(OpName)
<< OpVTStr << "(const SDValue &N) {\n";
<< OpVTStr << "(SDNode *N) {\n";
// Emit all of the patterns now, grouped together to share code.
EmitPatterns(CodeForPatterns, 2, OS);
@ -1906,11 +1933,11 @@ void DAGISelEmitter::EmitInstructionSelector(raw_ostream &OS) {
}
OS << "// The main instruction selector code.\n"
<< "SDNode *SelectCode(SDValue N) {\n"
<< " MVT::SimpleValueType NVT = N.getNode()->getValueType(0).getSimpleVT().SimpleTy;\n"
<< " switch (N.getOpcode()) {\n"
<< "SDNode *SelectCode(SDNode *N) {\n"
<< " MVT::SimpleValueType NVT = N->getValueType(0).getSimpleVT().SimpleTy;\n"
<< " switch (N->getOpcode()) {\n"
<< " default:\n"
<< " assert(!N.isMachineOpcode() && \"Node already selected!\");\n"
<< " assert(!N->isMachineOpcode() && \"Node already selected!\");\n"
<< " break;\n"
<< " case ISD::EntryToken: // These nodes remain the same.\n"
<< " case ISD::BasicBlock:\n"
@ -1932,7 +1959,7 @@ void DAGISelEmitter::EmitInstructionSelector(raw_ostream &OS) {
<< " }\n"
<< " case ISD::AssertSext:\n"
<< " case ISD::AssertZext: {\n"
<< " ReplaceUses(N, N.getOperand(0));\n"
<< " ReplaceUses(SDValue(N, 0), N->getOperand(0));\n"
<< " return NULL;\n"
<< " }\n"
<< " case ISD::INLINEASM: return Select_INLINEASM(N);\n"
@ -1999,9 +2026,9 @@ void DAGISelEmitter::EmitInstructionSelector(raw_ostream &OS) {
}
OS << " } // end of big switch.\n\n"
<< " if (N.getOpcode() != ISD::INTRINSIC_W_CHAIN &&\n"
<< " N.getOpcode() != ISD::INTRINSIC_WO_CHAIN &&\n"
<< " N.getOpcode() != ISD::INTRINSIC_VOID) {\n"
<< " if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&\n"
<< " N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&\n"
<< " N->getOpcode() != ISD::INTRINSIC_VOID) {\n"
<< " CannotYetSelect(N);\n"
<< " } else {\n"
<< " CannotYetSelectIntrinsic(N);\n"