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Wrap some lines to fix indentation problems.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68405 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-04-03 21:08:42 +00:00
parent 1b46a68015
commit eec4b2d730
1 changed files with 36 additions and 30 deletions
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32
lib/Target/ARM/ARMInstrInfo.cpp
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@ -25,7 +25,8 @@
#include "llvm/Support/CommandLine.h"
using namespace llvm;
static cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
static cl::opt<bool>
EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
cl::desc("Enable ARM 2-addr to 3-addr conv"));
static inline
@ -445,7 +446,8 @@ unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
return 2;
}
unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
unsigned
ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const {
// FIXME this should probably have a DebugLoc argument
@ -600,7 +602,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
}
}
void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
void ARMInstrInfo::
loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
@ -632,7 +635,8 @@ void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
return;
}
bool ARMInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
bool ARMInstrInfo::
spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const {
MachineFunction &MF = *MBB.getParent();
@ -653,7 +657,8 @@ bool ARMInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
return true;
}
bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
bool ARMInstrInfo::
restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const {
MachineFunction &MF = *MBB.getParent();
@ -679,10 +684,9 @@ bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
return true;
}
MachineInstr *ARMInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr *MI,
const SmallVectorImpl<unsigned> &Ops,
int FI) const {
MachineInstr *ARMInstrInfo::
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
const SmallVectorImpl<unsigned> &Ops, int FI) const {
if (Ops.size() != 1) return NULL;
unsigned OpNum = Ops[0];
@ -772,7 +776,8 @@ MachineInstr *ARMInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
return NewMI;
}
bool ARMInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
bool ARMInstrInfo::
canFoldMemoryOperand(const MachineInstr *MI,
const SmallVectorImpl<unsigned> &Ops) const {
if (Ops.size() != 1) return false;
@ -837,7 +842,8 @@ bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
}
bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
bool ARMInstrInfo::
PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Pred) const {
unsigned Opc = MI->getOpcode();
if (Opc == ARM::B || Opc == ARM::tB) {
@ -857,8 +863,8 @@ bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
return false;
}
bool
ARMInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
bool ARMInstrInfo::
SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const {
if (Pred1.size() > 2 || Pred2.size() > 2)
return false;