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Add some Book-E instructions to the asm parser and printer.

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Summary:
Adds the following instructions:
* mfpmr
* mtpmr
* icblc
* icblq
* icbtls

Fix the scheduling for mtspr on e5500, which uses CFX0, instead of
SFX0/SFX1 as on e500mc.

Addresses PR 31538.

Differential Revision: https://reviews.llvm.org/D29002

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293417 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Hibbits 2017-01-29 04:55:57 +00:00
parent a4249525ab
commit ef43506806
6 changed files with 52 additions and 3 deletions
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13
lib/Target/PowerPC/PPCInstrInfo.td
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@ -1508,8 +1508,14 @@ def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst),
PPC970_DGroup_Single;
} // hasSideEffects = 0
def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src),
"icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>;
def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src),
"icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
"icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src),
"icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
def : Pat<(int_ppc_dcbt xoaddr:$dst),
(DCBT 0, xoaddr:$dst)>;
@ -2379,6 +2385,13 @@ def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
"mftb $RT, $SPR", IIC_SprMFTB>;
def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR),
"mfpmr $RT, $SPR", IIC_SprMFPMR>;
def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT),
"mtpmr $SPR, $RT", IIC_SprMTPMR>;
// A pseudo-instruction used to implement the read of the 64-bit cycle counter
// on a 32-bit target.
let hasSideEffects = 1, usesCustomInserter = 1 in

2
lib/Target/PowerPC/PPCSchedule.td
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@ -118,6 +118,8 @@ def IIC_SprTLBIE : InstrItinClass;
def IIC_SprABORT : InstrItinClass;
def IIC_SprMSGSYNC : InstrItinClass;
def IIC_SprSTOP : InstrItinClass;
def IIC_SprMFPMR : InstrItinClass;
def IIC_SprMTPMR : InstrItinClass;
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.

8
lib/Target/PowerPC/PPCScheduleE500mc.td
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@ -249,6 +249,10 @@ def PPCE500mcItineraries : ProcessorItineraries<
InstrStage<5, [E500_SFX0]>],
[8, 1],
[E500_GPR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4
@ -257,6 +261,10 @@ def PPCE500mcItineraries : ProcessorItineraries<
InstrStage<1, [E500_SFX0, E500_SFX1]>],
[4, 1], // Latency = 1, Repeat rate = 1
[E500_GPR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0]>],
[4, 1], // Latency = 1, Repeat rate = 1
[E500_CR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4

10
lib/Target/PowerPC/PPCScheduleE5500.td
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@ -313,20 +313,24 @@ def PPCE5500Itineraries : ProcessorItineraries<
InstrStage<5, [E5500_CFX_0]>],
[9, 2], // Latency = 5, Repeat rate = 5
[E5500_GPR_Bypass, E5500_CR_Bypass]>,
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<4, [E5500_SFX0]>],
InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<4, [E5500_CFX_0]>],
[8, 2], // Latency = 4, Repeat rate = 4
[E5500_GPR_Bypass, E5500_GPR_Bypass]>,
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<1, [E5500_CFX_0]>],
[5], // Latency = 1, Repeat rate = 1
[E5500_GPR_Bypass]>,
InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<1, [E5500_CFX_0]>],
[5], // Latency = 1, Repeat rate = 1
[E5500_GPR_Bypass]>,
InstrItinData<IIC_SprMFTB, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<4, [E5500_CFX_0]>],
[8, 2], // Latency = 4, Repeat rate = 4
[NoBypass, E5500_GPR_Bypass]>,
InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
InstrStage<1, [E5500_CFX_0]>],
[5], // Latency = 1, Repeat rate = 1
[E5500_GPR_Bypass]>,
InstrItinData<IIC_FPGeneral, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,

9
test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt
View File

@ -134,3 +134,12 @@
0x7c 0x0b 0x66 0x24
# CHECK: tlbsx 11, 12
0x7c 0x0b 0x67 0x24
# CHECK: mfpmr 5, 400
0x7c 0xb0 0x62 0x9c
# CHECK: mtpmr 400, 6
0x7c 0xd0 0x63 0x9c
# CHECK: icblc 0, 0, 8
0x7c 0x00 0x41 0xcc
# CHECK: icbtls 0, 0, 9
0x7c 0x00 0x4b 0xcc

13
test/MC/PowerPC/ppc64-encoding-bookIII.s
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@ -197,3 +197,16 @@
# CHECK-BE: tlbsx 11, 12 # encoding: [0x7c,0x0b,0x67,0x24]
# CHECK-LE: tlbsx 11, 12 # encoding: [0x24,0x67,0x0b,0x7c]
tlbsx %r11, %r12
# CHECK-BE: mfpmr 5, 400 # encoding: [0x7c,0xb0,0x62,0x9c]
# CHECK-LE: mfpmr 5, 400 # encoding: [0x9c,0x62,0xb0,0x7c]
mfpmr 5, 400
# CHECK-BE: mtpmr 400, 6 # encoding: [0x7c,0xd0,0x63,0x9c]
# CHECK-LE: mtpmr 400, 6 # encoding: [0x9c,0x63,0xd0,0x7c]
mtpmr 400, 6
# CHECK-BE: icblc 0, 0, 8 # encoding: [0x7c,0x00,0x41,0xcc]
# CHECK-LE: icblc 0, 0, 8 # encoding: [0xcc,0x41,0x00,0x7c]
icblc 0, 0, 8
# CHECK-BE: icbtls 0, 0, 9 # encoding: [0x7c,0x00,0x4b,0xcc]
# CHECK-LE: icbtls 0, 0, 9 # encoding: [0xcc,0x4b,0x00,0x7c]
icbtls 0, 0, 9