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[ARM] More care with Thumb1 writeback in ARMLoadStoreOptimizer

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Differential Revision: http://reviews.llvm.org/D13240

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249002 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Scott Douglass 2015-10-01 11:56:19 +00:00
parent fd5a6e2618
commit efd63253a8
2 changed files with 34 additions and 3 deletions
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10
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -630,9 +630,10 @@ MachineInstr *ARMLoadStoreOpt::CreateLoadStoreMulti(MachineBasicBlock &MBB,
unsigned NewBase;
if (isi32Load(Opcode)) {
// If it is a load, then just use one of the destination register to
// use as the new base.
// If it is a load, then just use one of the destination registers
// as the new base. Will no longer be writeback in Thumb1.
NewBase = Regs[NumRegs-1].first;
Writeback = false;
} else {
// Find a free register that we can use as scratch register.
moveLiveRegsBefore(MBB, InsertBefore);
@ -736,9 +737,12 @@ MachineInstr *ARMLoadStoreOpt::CreateLoadStoreMulti(MachineBasicBlock &MBB,
MachineInstrBuilder MIB;
if (Writeback) {
if (Opcode == ARM::tLDMIA)
assert(isThumb1 && "expected Writeback only inThumb1");
if (Opcode == ARM::tLDMIA) {
assert(!(ContainsReg(Regs, Base)) && "Thumb1 can't LDM ! with Base in Regs");
// Update tLDMIA with writeback if necessary.
Opcode = ARM::tLDMIA_UPD;
}
MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));

27
test/CodeGen/ARM/thumb1-ldst-opt.ll Normal file
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@ -0,0 +1,27 @@
; RUN: llc -stop-after block-placement -o /dev/null %s | FileCheck %s
target triple = "thumbv6m-none-none"
define i32* @foo(i32* readonly %p0) {
entry:
%add.ptr = getelementptr inbounds i32, i32* %p0, i32 10
%arrayidx = getelementptr inbounds i32, i32* %p0, i32 13
%0 = load i32, i32* %arrayidx, align 4
%arrayidx1 = getelementptr inbounds i32, i32* %p0, i32 12
%1 = load i32, i32* %arrayidx1, align 4
%add = add nsw i32 %1, %0
%arrayidx2 = getelementptr inbounds i32, i32* %p0, i32 11
%2 = load i32, i32* %arrayidx2, align 4
%add3 = add nsw i32 %add, %2
%3 = load i32, i32* %add.ptr, align 4
%add5 = add nsw i32 %add3, %3
tail call void @g(i32 %add5)
ret i32* %p0
}
declare void @g(i32)
; CHECK-LABEL: name: foo
; CHECK: [[BASE:%r[0-7]]], {{.*}} tADDi8
; CHECK-NOT: [[BASE]] = tLDMIA_UPD {{.*}} [[BASE]]
; CHECK: tLDMIA killed [[BASE]], {{.*}} def [[BASE]]