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while we're at it, handle 'sdiv exact' of a power of 2 also,

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this fixes a few rejects on c++ iterator loops.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129694 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2011-04-18 07:00:40 +00:00
parent 090ca9108b
commit f051c1a29d
2 changed files with 16 additions and 0 deletions
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8
lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -360,6 +360,14 @@ bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) {
if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
uint64_t Imm = CI->getZExtValue();
// Transform "sdiv exact X, 8" -> "sra X, 3".
if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
cast<BinaryOperator>(I)->isExact() &&
isPowerOf2_64(Imm)) {
Imm = Log2_64(Imm);
ISDOpcode = ISD::SRA;
}
unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
Op0IsKill, Imm, VT.getSimpleVT());
if (ResultReg == 0) return false;

8
test/CodeGen/X86/fast-isel-x86-64.ll
View File

@ -119,3 +119,11 @@ define i32 @test10(i32 %X) nounwind {
; CHECK: test10:
; CHECK: shrl $3,
}
define i32 @test11(i32 %X) nounwind {
%Y = sdiv exact i32 %X, 8
ret i32 %Y
; CHECK: test11:
; CHECK: sarl $3,
}