mirror of
https://github.com/RPCSX/llvm.git
synced 2024-11-30 07:00:45 +00:00
rip out the 'heinous' x86 MCCodeEmitter implementation.
We still have the templated X86 JIT emitter, *and* the almost-copy in X86InstrInfo for getting instruction sizes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96059 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
a599de2410
commit
f068304b1f
@ -50,8 +50,6 @@ FunctionPass *createX87FPRegKillInserterPass();
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FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM,
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JITCodeEmitter &JCE);
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MCCodeEmitter *createHeinousX86MCCodeEmitter(const Target &, TargetMachine &TM,
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MCContext &Ctx);
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MCCodeEmitter *createX86_32MCCodeEmitter(const Target &, TargetMachine &TM,
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MCContext &Ctx);
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MCCodeEmitter *createX86_64MCCodeEmitter(const Target &, TargetMachine &TM,
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@ -871,336 +871,3 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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MCE.processDebugLoc(MI.getDebugLoc(), false);
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}
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// Adapt the Emitter / CodeEmitter interfaces to MCCodeEmitter.
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//
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// FIXME: This is a total hack designed to allow work on llvm-mc to proceed
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// without being blocked on various cleanups needed to support a clean interface
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// to instruction encoding.
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//
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// Look away!
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#include "llvm/DerivedTypes.h"
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namespace {
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class MCSingleInstructionCodeEmitter : public MachineCodeEmitter {
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uint8_t Data[256];
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const MCInst *CurrentInst;
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SmallVectorImpl<MCFixup> *FixupList;
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public:
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MCSingleInstructionCodeEmitter() { reset(0, 0); }
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void reset(const MCInst *Inst, SmallVectorImpl<MCFixup> *Fixups) {
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CurrentInst = Inst;
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FixupList = Fixups;
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BufferBegin = Data;
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BufferEnd = array_endof(Data);
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CurBufferPtr = Data;
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}
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StringRef str() {
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return StringRef(reinterpret_cast<char*>(BufferBegin),
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CurBufferPtr - BufferBegin);
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}
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virtual void startFunction(MachineFunction &F) {}
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virtual bool finishFunction(MachineFunction &F) { return false; }
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virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) {}
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virtual bool earlyResolveAddresses() const { return false; }
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virtual void addRelocation(const MachineRelocation &MR) {
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unsigned Offset = 0, OpIndex = 0, Kind = MR.getRelocationType();
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// This form is only used in one case, for branches.
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if (MR.isBasicBlock()) {
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Offset = unsigned(MR.getMachineCodeOffset());
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OpIndex = 0;
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} else {
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assert(MR.isJumpTableIndex() && "Unexpected relocation!");
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Offset = unsigned(MR.getMachineCodeOffset());
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// The operand index is encoded as the first byte of the fake operand.
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OpIndex = MR.getJumpTableIndex();
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}
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MCOperand Op = CurrentInst->getOperand(OpIndex);
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assert(Op.isExpr() && "FIXME: Not yet implemented!");
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FixupList->push_back(MCFixup::Create(Offset, Op.getExpr(),
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MCFixupKind(FirstTargetFixupKind + Kind)));
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}
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virtual void setModuleInfo(MachineModuleInfo* Info) {}
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// Interface functions which should never get called in our usage.
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virtual void emitLabel(uint64_t LabelID) {
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assert(0 && "Unexpected code emitter call!");
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}
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virtual uintptr_t getConstantPoolEntryAddress(unsigned Index) const {
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assert(0 && "Unexpected code emitter call!");
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return 0;
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}
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virtual uintptr_t getJumpTableEntryAddress(unsigned Index) const {
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assert(0 && "Unexpected code emitter call!");
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return 0;
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}
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virtual uintptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const {
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assert(0 && "Unexpected code emitter call!");
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return 0;
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}
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virtual uintptr_t getLabelAddress(uint64_t LabelID) const {
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assert(0 && "Unexpected code emitter call!");
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return 0;
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}
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};
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class X86MCCodeEmitter : public MCCodeEmitter {
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X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
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void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
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private:
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X86TargetMachine &TM;
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llvm::Function *DummyF;
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TargetData *DummyTD;
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mutable llvm::MachineFunction *DummyMF;
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llvm::MachineBasicBlock *DummyMBB;
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MCSingleInstructionCodeEmitter *InstrEmitter;
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Emitter<MachineCodeEmitter> *Emit;
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public:
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X86MCCodeEmitter(X86TargetMachine &_TM) : TM(_TM) {
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// Verily, thou shouldst avert thine eyes.
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const llvm::FunctionType *FTy =
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FunctionType::get(llvm::Type::getVoidTy(getGlobalContext()), false);
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DummyF = Function::Create(FTy, GlobalValue::InternalLinkage);
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DummyTD = new TargetData("");
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DummyMF = new MachineFunction(DummyF, TM, 0);
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DummyMBB = DummyMF->CreateMachineBasicBlock();
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InstrEmitter = new MCSingleInstructionCodeEmitter();
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Emit = new Emitter<MachineCodeEmitter>(TM, *InstrEmitter,
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*TM.getInstrInfo(),
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*DummyTD, false);
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}
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~X86MCCodeEmitter() {
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delete Emit;
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delete InstrEmitter;
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delete DummyMF;
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delete DummyF;
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}
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unsigned getNumFixupKinds() const {
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return 5;
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}
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MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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static MCFixupKindInfo Infos[] = {
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{ "reloc_pcrel_word", 0, 4 * 8 },
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{ "reloc_picrel_word", 0, 4 * 8 },
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{ "reloc_absolute_word", 0, 4 * 8 },
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{ "reloc_absolute_word_sext", 0, 4 * 8 },
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{ "reloc_absolute_dword", 0, 8 * 8 }
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};
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assert(Kind >= FirstTargetFixupKind && Kind < MaxTargetFixupKind &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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bool AddRegToInstr(const MCInst &MI, MachineInstr *Instr,
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unsigned Start) const {
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if (Start + 1 > MI.getNumOperands())
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return false;
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const MCOperand &Op = MI.getOperand(Start);
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if (!Op.isReg()) return false;
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Instr->addOperand(MachineOperand::CreateReg(Op.getReg(), false));
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return true;
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}
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bool AddImmToInstr(const MCInst &MI, MachineInstr *Instr,
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unsigned Start) const {
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if (Start + 1 > MI.getNumOperands())
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return false;
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const MCOperand &Op = MI.getOperand(Start);
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if (Op.isImm()) {
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Instr->addOperand(MachineOperand::CreateImm(Op.getImm()));
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return true;
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}
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if (!Op.isExpr())
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return false;
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const MCExpr *Expr = Op.getExpr();
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if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
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Instr->addOperand(MachineOperand::CreateImm(CE->getValue()));
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return true;
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}
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// Fake this as an external symbol to the code emitter to add a relcoation
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// entry we will recognize.
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Instr->addOperand(MachineOperand::CreateJTI(Start, 0));
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return true;
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}
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bool AddLMemToInstr(const MCInst &MI, MachineInstr *Instr,
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unsigned Start) const {
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return (AddRegToInstr(MI, Instr, Start + 0) &&
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AddImmToInstr(MI, Instr, Start + 1) &&
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AddRegToInstr(MI, Instr, Start + 2) &&
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AddImmToInstr(MI, Instr, Start + 3));
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}
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bool AddMemToInstr(const MCInst &MI, MachineInstr *Instr,
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unsigned Start) const {
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return (AddRegToInstr(MI, Instr, Start + 0) &&
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AddImmToInstr(MI, Instr, Start + 1) &&
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AddRegToInstr(MI, Instr, Start + 2) &&
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AddImmToInstr(MI, Instr, Start + 3) &&
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AddRegToInstr(MI, Instr, Start + 4));
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}
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// Don't look yet!
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// Convert the MCInst to a MachineInstr so we can (ab)use the regular
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// emitter.
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const X86InstrInfo &II = *TM.getInstrInfo();
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const TargetInstrDesc &Desc = II.get(MI.getOpcode());
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MachineInstr *Instr = DummyMF->CreateMachineInstr(Desc, DebugLoc());
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DummyMBB->push_back(Instr);
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unsigned Opcode = MI.getOpcode();
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unsigned NumOps = MI.getNumOperands();
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unsigned CurOp = 0;
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bool AddTied = false;
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if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
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AddTied = true;
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else if (NumOps > 2 &&
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Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
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// Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
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--NumOps;
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bool OK = true;
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::MRMDestReg:
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case X86II::MRMSrcReg:
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// Matching doesn't fill this in completely, we have to choose operand 0
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// for a tied register.
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OK &= AddRegToInstr(MI, Instr, CurOp++);
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if (AddTied)
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OK &= AddRegToInstr(MI, Instr, CurOp++ - 1);
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OK &= AddRegToInstr(MI, Instr, CurOp++);
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if (CurOp < NumOps)
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OK &= AddImmToInstr(MI, Instr, CurOp);
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break;
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case X86II::RawFrm:
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if (CurOp < NumOps) {
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// Hack to make branches work.
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if (!(Desc.TSFlags & X86II::ImmMask) &&
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MI.getOperand(0).isExpr() &&
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isa<MCSymbolRefExpr>(MI.getOperand(0).getExpr()))
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Instr->addOperand(MachineOperand::CreateMBB(DummyMBB));
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else
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OK &= AddImmToInstr(MI, Instr, CurOp);
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}
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break;
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case X86II::AddRegFrm:
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// Matching doesn't fill this in completely, we have to choose operand 0
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// for a tied register.
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OK &= AddRegToInstr(MI, Instr, CurOp++);
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if (AddTied)
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OK &= AddRegToInstr(MI, Instr, CurOp++ - 1);
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if (CurOp < NumOps)
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OK &= AddImmToInstr(MI, Instr, CurOp);
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break;
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case X86II::MRM0r: case X86II::MRM1r:
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case X86II::MRM2r: case X86II::MRM3r:
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case X86II::MRM4r: case X86II::MRM5r:
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case X86II::MRM6r: case X86II::MRM7r:
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// Matching doesn't fill this in completely, we have to choose operand 0
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// for a tied register.
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OK &= AddRegToInstr(MI, Instr, CurOp++);
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if (AddTied)
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OK &= AddRegToInstr(MI, Instr, CurOp++ - 1);
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if (CurOp < NumOps)
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OK &= AddImmToInstr(MI, Instr, CurOp);
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break;
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case X86II::MRM0m: case X86II::MRM1m:
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case X86II::MRM2m: case X86II::MRM3m:
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case X86II::MRM4m: case X86II::MRM5m:
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case X86II::MRM6m: case X86II::MRM7m:
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OK &= AddMemToInstr(MI, Instr, CurOp); CurOp += 5;
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if (CurOp < NumOps)
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OK &= AddImmToInstr(MI, Instr, CurOp);
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break;
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case X86II::MRMSrcMem:
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// Matching doesn't fill this in completely, we have to choose operand 0
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// for a tied register.
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OK &= AddRegToInstr(MI, Instr, CurOp++);
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if (AddTied)
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OK &= AddRegToInstr(MI, Instr, CurOp++ - 1);
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if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
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Opcode == X86::LEA16r || Opcode == X86::LEA32r)
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OK &= AddLMemToInstr(MI, Instr, CurOp);
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else
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OK &= AddMemToInstr(MI, Instr, CurOp);
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break;
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case X86II::MRMDestMem:
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OK &= AddMemToInstr(MI, Instr, CurOp); CurOp += 5;
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OK &= AddRegToInstr(MI, Instr, CurOp);
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break;
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default:
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case X86II::MRMInitReg:
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case X86II::Pseudo:
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OK = false;
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break;
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}
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if (!OK) {
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dbgs() << "couldn't convert inst '";
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MI.dump();
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dbgs() << "' to machine instr:\n";
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Instr->dump();
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}
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InstrEmitter->reset(&MI, &Fixups);
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if (OK)
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Emit->emitInstruction(*Instr, &Desc);
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OS << InstrEmitter->str();
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Instr->eraseFromParent();
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}
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};
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}
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#include "llvm/Support/CommandLine.h"
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static cl::opt<bool> EnableNewEncoder("enable-new-x86-encoder",
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cl::ReallyHidden);
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// Ok, now you can look.
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MCCodeEmitter *llvm::createHeinousX86MCCodeEmitter(const Target &T,
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TargetMachine &TM,
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MCContext &Ctx) {
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// FIXME: Remove the heinous one when the new one works.
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if (EnableNewEncoder) {
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if (TM.getTargetData()->getPointerSize() == 4)
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return createX86_32MCCodeEmitter(T, TM, Ctx);
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return createX86_64MCCodeEmitter(T, TM, Ctx);
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}
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return new X86MCCodeEmitter(static_cast<X86TargetMachine&>(TM));
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}
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@ -48,11 +48,10 @@ extern "C" void LLVMInitializeX86Target() {
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RegisterAsmInfoFn B(TheX86_64Target, createMCAsmInfo);
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// Register the code emitter.
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// FIXME: Remove the heinous one when the new one works.
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TargetRegistry::RegisterCodeEmitter(TheX86_32Target,
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createHeinousX86MCCodeEmitter);
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createX86_32MCCodeEmitter);
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TargetRegistry::RegisterCodeEmitter(TheX86_64Target,
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createHeinousX86MCCodeEmitter);
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createX86_64MCCodeEmitter);
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}
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@ -1,4 +1,4 @@
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// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding --enable-new-x86-encoder %s | FileCheck %s
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// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
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lfence
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// CHECK: lfence
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@ -1,4 +1,4 @@
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// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding --enable-new-x86-encoder %s | FileCheck %s
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// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
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movl foo(%rip), %eax
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// CHECK: movl foo(%rip), %eax
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Reference in New Issue
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