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Make TwoAddressInstructionPass::rescheduleMIBelowKill subreg-aware
This fixes PR28824. Differential Revision: https://reviews.llvm.org/D23220 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278370 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -29,7 +29,7 @@
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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@ -539,6 +539,16 @@ regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
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return TRI->regsOverlap(RegA, RegB);
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}
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// Returns true if Reg is equal or aliased to at least one register in Set.
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static bool regOverlapsSet(const SmallVectorImpl<unsigned> &Set, unsigned Reg,
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const TargetRegisterInfo *TRI) {
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for (unsigned R : Set)
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if (TRI->regsOverlap(R, Reg))
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return true;
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return false;
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}
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/// Return true if it's potentially profitable to commute the two-address
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/// instruction that's being processed.
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bool
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@ -864,9 +874,9 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
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// FIXME: Needs more sophisticated heuristics.
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return false;
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SmallSet<unsigned, 2> Uses;
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SmallSet<unsigned, 2> Kills;
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SmallSet<unsigned, 2> Defs;
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SmallVector<unsigned, 2> Uses;
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SmallVector<unsigned, 2> Kills;
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SmallVector<unsigned, 2> Defs;
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for (const MachineOperand &MO : MI->operands()) {
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if (!MO.isReg())
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continue;
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@ -874,12 +884,12 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
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if (!MOReg)
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continue;
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if (MO.isDef())
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Defs.insert(MOReg);
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Defs.push_back(MOReg);
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else {
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Uses.insert(MOReg);
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Uses.push_back(MOReg);
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if (MOReg != Reg && (MO.isKill() ||
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(LIS && isPlainlyKilled(MI, MOReg, LIS))))
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Kills.insert(MOReg);
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Kills.push_back(MOReg);
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}
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}
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@ -888,8 +898,9 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator AfterMI = std::next(Begin);
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MachineBasicBlock::iterator End = AfterMI;
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while (End->isCopy() && Defs.count(End->getOperand(1).getReg())) {
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Defs.insert(End->getOperand(0).getReg());
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while (End->isCopy() &&
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regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI)) {
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Defs.push_back(End->getOperand(0).getReg());
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++End;
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}
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@ -915,21 +926,21 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
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if (!MOReg)
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continue;
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if (MO.isDef()) {
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if (Uses.count(MOReg))
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if (regOverlapsSet(Uses, MOReg, TRI))
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// Physical register use would be clobbered.
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return false;
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if (!MO.isDead() && Defs.count(MOReg))
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if (!MO.isDead() && regOverlapsSet(Defs, MOReg, TRI))
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// May clobber a physical register def.
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// FIXME: This may be too conservative. It's ok if the instruction
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// is sunken completely below the use.
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return false;
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} else {
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if (Defs.count(MOReg))
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if (regOverlapsSet(Defs, MOReg, TRI))
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return false;
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bool isKill =
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MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS));
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if (MOReg != Reg &&
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((isKill && Uses.count(MOReg)) || Kills.count(MOReg)))
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if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg, TRI)) ||
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regOverlapsSet(Kills, MOReg, TRI)))
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// Don't want to extend other live ranges and update kills.
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return false;
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if (MOReg == Reg && !isKill)
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23
test/CodeGen/X86/pr28824.ll
Normal file
23
test/CodeGen/X86/pr28824.ll
Normal file
@ -0,0 +1,23 @@
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; RUN: llc < %s -mtriple=i386-unknown-linux-gnu | FileCheck %s
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@d = global i32 0, align 4
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; Verify the sar happens before ecx is clobbered with the parameter being
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; passed to fn3
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; CHECK-LABEL: fn4
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; CHECK: movb d, %cl
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; CHECK: sarl %cl
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; CHECK: movl $2, %ecx
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define i32 @fn4(i32 %i) #0 {
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entry:
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%0 = load i32, i32* @d, align 4
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%shr = ashr i32 %i, %0
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tail call fastcc void @fn3(i32 2, i32 5, i32 %shr, i32 %i)
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%cmp = icmp slt i32 %shr, 1
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%. = zext i1 %cmp to i32
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ret i32 %.
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}
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declare void @fn3(i32 %p1, i32 %p2, i32 %p3, i32 %p4) #0
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attributes #0 = { nounwind }
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