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ARM assembly parsing and encoding tests for TEQ instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136259 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-07-27 20:37:36 +00:00
parent 06470311c5
commit f1ae78af17
1 changed files with 34 additions and 0 deletions
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34
test/MC/ARM/basic-arm-instructions.s
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@ -1914,3 +1914,37 @@ _func:
@ encoding: [0x72,0x28,0xbf,0xd6]
@ CHECK: sxth r9, r3, ror #24
@ encoding: [0x73,0x9c,0xbf,0xe6]
@------------------------------------------------------------------------------
@ FIXME: TBB/TBH
@------------------------------------------------------------------------------
@------------------------------------------------------------------------------
@ TEQ
@------------------------------------------------------------------------------
teq r5, #0xf000
teq r4, r5
teq r4, r5, lsl #5
teq r4, r5, lsr #5
teq r4, r5, lsr #5
teq r4, r5, asr #5
teq r4, r5, ror #5
teq r6, r7, lsl r9
teq r6, r7, lsr r9
teq r6, r7, asr r9
teq r6, r7, ror r9
@ CHECK: teq r5, #61440 @ encoding: [0x0f,0x0a,0x35,0xe3]
@ CHECK: teq r4, r5 @ encoding: [0x05,0x00,0x34,0xe1]
@ CHECK: teq r4, r5, lsl #5 @ encoding: [0x85,0x02,0x34,0xe1]
@ CHECK: teq r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x34,0xe1]
@ CHECK: teq r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x34,0xe1]
@ CHECK: teq r4, r5, asr #5 @ encoding: [0xc5,0x02,0x34,0xe1]
@ CHECK: teq r4, r5, ror #5 @ encoding: [0xe5,0x02,0x34,0xe1]
@ CHECK: teq r6, r7, lsl r9 @ encoding: [0x17,0x09,0x36,0xe1]
@ CHECK: teq r6, r7, lsr r9 @ encoding: [0x37,0x09,0x36,0xe1]
@ CHECK: teq r6, r7, asr r9 @ encoding: [0x57,0x09,0x36,0xe1]
@ CHECK: teq r6, r7, ror r9 @ encoding: [0x77,0x09,0x36,0xe1]