RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-14 15:39:00 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[ARM CodeGen] @llvm.debugtrap call may be removed when restoring callee saved registers

Browse Source 
Summary:
When ARMFrameLowering::emitPopInst generates a "pop" instruction to restore the callee saved registers, it checks if the LR register is among them. If so, the function may decide to remove the basic block's terminator and replace it with a "pop" to the PC register instead of LR.

This leads to a problem when the block's terminator is preceded by a "llvm.debugtrap" call. The MI iterator points to the trap in such a case, which is also a terminator. If the function decides to restore LR to PC, it erroneously removes the trap.

Reviewers: asl, rengolin

Subscribers: aemerson, jfb, rengolin, dschuff, llvm-commits

Differential Revision: http://reviews.llvm.org/D13672

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251123 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Oleg Ranevskyy 2015-10-23 17:17:59 +00:00
parent cd69ab5ddf
commit f1c16763a7
2 changed files with 22 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/ARM/ARMFrameLowering.cpp
View File

@ -968,12 +968,16 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
DebugLoc DL;
bool isTailCall = false;
bool isInterrupt = false;
bool isTrap = false;
if (MBB.end() != MI) {
DL = MI->getDebugLoc();
unsigned RetOpcode = MI->getOpcode();
isTailCall = (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri);
isInterrupt =
RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
isTrap =
RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl ||
RetOpcode == ARM::tTRAP;
}
SmallVector<unsigned, 4> Regs;
@ -990,7 +994,7 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
continue;
if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
STI.hasV5TOps()) {
!isTrap && STI.hasV5TOps()) {
if (MBB.succ_empty()) {
Reg = ARM::PC;
DeleteRet = true;

17
test/CodeGen/ARM/debugtrap.ll Normal file
View File

@ -0,0 +1,17 @@
; This test ensures the @llvm.debugtrap() call is not removed when generating
; the 'pop' instruction to restore the callee saved registers on ARM.
; RUN: llc < %s -mtriple=armv7 -O0 -filetype=asm | FileCheck %s
declare void @llvm.debugtrap() nounwind
declare void @foo() nounwind
define void @test() nounwind {
entry:
; CHECK: bl foo
; CHECK-NEXT: pop
; CHECK-NEXT: trap
call void @foo()
call void @llvm.debugtrap()
ret void
}