RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-13 23:18:51 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Reenable DAG combining for vector shuffles. It looks like it was temporarily

Browse Source 
disabled and then never turned back on again.  Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-07-09 00:38:12 +00:00
parent 757e8d6d2e
commit f1d93ca920
3 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -6309,8 +6309,6 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
}
SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
return SDValue();
EVT VT = N->getValueType(0);
unsigned NumElts = VT.getVectorNumElements();

21
test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
View File

@ -4,19 +4,22 @@ target triple = "thumbv7-apple-darwin10"
; This tests the fast register allocator's handling of partial redefines:
;
; %reg1026<def> = VMOVv16i8 0, pred:14, pred:%reg0
; %reg1028:dsub_1<def> = EXTRACT_SUBREG %reg1026<kill>, 1
; %reg1028:dsub_0<def>, %reg1028:dsub_1<def> = VLD1q64 %reg1025...
; %reg1030:dsub_1<def> = COPY %reg1028:dsub_0<kill>
;
; %reg1026 gets allocated %Q0, and if %reg1028 is reloaded for the partial redef,
; it cannot also get %Q0.
; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial
; redef, it cannot also get %Q0.
; CHECK: vmov.i8 q0, #0x0
; CHECK-NOT: vld1.64 {d0,d1}
; CHECK: vld1.64 {d0, d1}, [r0]
; CHECK-NOT: vld1.64 {d0, d1}
; CHECK: vmov.f64 d3, d0
define i32 @main(i32 %argc, i8** %argv) nounwind {
define i32 @test(i8* %arg) nounwind {
entry:
%0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1]
store <2 x i64> %0, <2 x i64>* undef, align 16
%0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %arg)
%1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32> <i32 1, i32 2>
store <2 x i64> %1, <2 x i64>* undef, align 16
ret i32 undef
}
declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*) nounwind readonly

1
test/CodeGen/ARM/reg_sequence.ll
View File

@ -270,7 +270,6 @@ define arm_aapcs_vfpcc i32 @t10() nounwind {
entry:
; CHECK: t10:
; CHECK: vmov.i32 q1, #0x3F000000
; CHECK: vdup.32 q0, d0[0]
; CHECK: vmov d0, d1
; CHECK: vmla.f32 q0, q0, d0[0]
%0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]