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ARM: Better codegen for 64-bit compares.
This introduces a custom lowering for ISD::SETCCE (introduced in r253572)
that allows us to emit a short code sequence for 64-bit compares.
Before:
push {r7, lr}
cmp r0, r2
mov.w r0, #0
mov.w r12, #0
it hs
movhs r0, #1
cmp r1, r3
it ge
movge.w r12, #1
it eq
moveq r12, r0
cmp.w r12, #0
bne .LBB1_2
@ BB#1: @ %bb1
bl f
pop {r7, pc}
.LBB1_2: @ %bb2
bl g
pop {r7, pc}
After:
push {r7, lr}
subs r0, r0, r2
sbcs.w r0, r1, r3
bge .LBB1_2
@ BB#1: @ %bb1
bl f
pop {r7, pc}
.LBB1_2: @ %bb2
bl g
pop {r7, pc}
Saves around 80KB in Chromium's libchrome.so.
Some notes on this patch:
- I don't much like the ARMISD::BRCOND and ARMISD::CMOV combines I
introduced (nothing else needs them). However, they are necessary in
order to avoid poor codegen, and they seem similar to existing combines
in other backends (e.g. X86 combines (brcond (cmp (setcc Compare))) to
(brcond Compare)).
- No support for Thumb-1. This is in principle possible, but we'd need
to implement ARMISD::SUBE for Thumb-1.
Differential Revision: http://reviews.llvm.org/D15256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263962 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Peter Collingbourne
parent
faf3d27a21
commit
f24c9d47b6
@ -919,6 +919,10 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
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// Thumb-1 cannot currently select ARMISD::SUBE.
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if (!Subtarget->isThumb1Only())
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setOperationAction(ISD::SETCCE, MVT::i32, Custom);
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f32, Custom);
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@ -4898,6 +4902,30 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
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return Result;
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}
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static SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) {
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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SDValue Carry = Op.getOperand(2);
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SDValue Cond = Op.getOperand(3);
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SDLoc DL(Op);
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assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
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assert(Carry.getOpcode() != ISD::CARRY_FALSE);
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SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
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SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry);
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SDValue FVal = DAG.getConstant(0, DL, MVT::i32);
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SDValue TVal = DAG.getConstant(1, DL, MVT::i32);
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SDValue ARMcc = DAG.getConstant(
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IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL, MVT::i32);
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SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,
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Cmp.getValue(1), SDValue());
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return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
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CCR, Chain.getValue(1));
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}
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/// isNEONModifiedImm - Check if the specified splat value corresponds to a
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/// valid vector constant for a NEON instruction with a "modified immediate"
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/// operand (e.g., VMOV). If so, return the encoded value.
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@ -7013,6 +7041,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
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case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
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case ISD::SETCC: return LowerVSETCC(Op, DAG);
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case ISD::SETCCE: return LowerSETCCE(Op, DAG);
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case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
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case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
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case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
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@ -10639,6 +10668,46 @@ SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &D
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return V;
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}
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/// PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND.
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SDValue
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ARMTargetLowering::PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const {
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SDValue Cmp = N->getOperand(4);
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if (Cmp.getOpcode() != ARMISD::CMPZ)
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// Only looking at NE cases.
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return SDValue();
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EVT VT = N->getValueType(0);
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SDLoc dl(N);
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SDValue LHS = Cmp.getOperand(0);
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SDValue RHS = Cmp.getOperand(1);
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SDValue Chain = N->getOperand(0);
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SDValue BB = N->getOperand(1);
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SDValue ARMcc = N->getOperand(2);
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ARMCC::CondCodes CC =
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(ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
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// (brcond Chain BB ne CPSR (cmpz (and (cmov 0 1 CC CPSR Cmp) 1) 0))
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// -> (brcond Chain BB CC CPSR Cmp)
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if (CC == ARMCC::NE && LHS.getOpcode() == ISD::AND && LHS->hasOneUse() &&
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LHS->getOperand(0)->getOpcode() == ARMISD::CMOV &&
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LHS->getOperand(0)->hasOneUse()) {
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auto *LHS00C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)->getOperand(0));
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auto *LHS01C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)->getOperand(1));
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auto *LHS1C = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
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auto *RHSC = dyn_cast<ConstantSDNode>(RHS);
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if ((LHS00C && LHS00C->getZExtValue() == 0) &&
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(LHS01C && LHS01C->getZExtValue() == 1) &&
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(LHS1C && LHS1C->getZExtValue() == 1) &&
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(RHSC && RHSC->getZExtValue() == 0)) {
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return DAG.getNode(
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ARMISD::BRCOND, dl, VT, Chain, BB, LHS->getOperand(0)->getOperand(2),
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LHS->getOperand(0)->getOperand(3), LHS->getOperand(0)->getOperand(4));
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}
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}
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return SDValue();
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}
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/// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
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SDValue
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ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
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@ -10692,6 +10761,21 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
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N->getOperand(3), NewCmp);
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}
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// (cmov F T ne CPSR (cmpz (cmov 0 1 CC CPSR Cmp) 0))
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// -> (cmov F T CC CPSR Cmp)
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if (CC == ARMCC::NE && LHS.getOpcode() == ARMISD::CMOV && LHS->hasOneUse()) {
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auto *LHS0C = dyn_cast<ConstantSDNode>(LHS->getOperand(0));
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auto *LHS1C = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
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auto *RHSC = dyn_cast<ConstantSDNode>(RHS);
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if ((LHS0C && LHS0C->getZExtValue() == 0) &&
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(LHS1C && LHS1C->getZExtValue() == 1) &&
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(RHSC && RHSC->getZExtValue() == 0)) {
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return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
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LHS->getOperand(2), LHS->getOperand(3),
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LHS->getOperand(4));
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}
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}
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if (Res.getNode()) {
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APInt KnownZero, KnownOne;
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DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
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@ -10742,6 +10826,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::ZERO_EXTEND:
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case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
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case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
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case ARMISD::BRCOND: return PerformBRCONDCombine(N, DCI.DAG);
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case ISD::LOAD: return PerformLOADCombine(N, DCI);
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case ARMISD::VLD2DUP:
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case ARMISD::VLD3DUP:
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@ -258,6 +258,7 @@ namespace llvm {
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SDNode *Node) const override;
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SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
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SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
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SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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@ -251,21 +251,18 @@ define i64 @test10(i64* %ptr, i64 %val) {
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; CHECK-LABEL: test10:
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; CHECK: dmb {{ish$}}
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
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; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
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; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
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; CHECK-LE: cmp [[REG1]], r1
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; CHECK-BE: cmp [[REG2]], r2
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; CHECK: movwls [[CARRY_LO]], #1
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; CHECK-LE: cmp [[REG2]], r2
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; CHECK-BE: cmp [[REG1]], r1
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; CHECK: movwle [[CARRY_HI]], #1
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; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
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; CHECK: cmp [[CARRY_HI]], #0
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; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]
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; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
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; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
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; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
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; CHECK: mov [[CMP:[a-z0-9]+]], #0
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; CHECK: movwge [[CMP]], #1
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; CHECK: cmp [[CMP]], #0
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; CHECK: movne [[OUT_HI]], [[REG2]]
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; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
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; CHECK: movne [[OUT_LO]], [[REG1]]
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb {{ish$}}
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@ -273,21 +270,18 @@ define i64 @test10(i64* %ptr, i64 %val) {
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; CHECK-THUMB-LABEL: test10:
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; CHECK-THUMB: dmb {{ish$}}
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+|lr]], #0
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; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+|lr]], #0
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; CHECK-THUMB-LE: cmp [[REG1]], r2
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; CHECK-THUMB-BE: cmp [[REG2]], r3
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; CHECK-THUMB: movls.w [[CARRY_LO]], #1
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; CHECK-THUMB-LE: cmp [[REG2]], r3
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; CHECK-THUMB-BE: cmp [[REG1]], r2
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; CHECK-THUMB: movle [[CARRY_HI]], #1
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; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
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; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
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; CHECK-THUMB: cmp [[CARRY_HI]], #0
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; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
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; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
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; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]
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; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
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; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
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; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
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; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0
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; CHECK-THUMB: movge.w [[CMP]], #1
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; CHECK-THUMB: cmp.w [[CMP]], #0
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; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
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; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
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; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb {{ish$}}
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@ -300,21 +294,18 @@ define i64 @test11(i64* %ptr, i64 %val) {
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; CHECK-LABEL: test11:
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; CHECK: dmb {{ish$}}
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
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; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
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; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
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; CHECK-LE: cmp [[REG1]], r1
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; CHECK-BE: cmp [[REG2]], r2
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; CHECK: movwls [[CARRY_LO]], #1
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; CHECK-LE: cmp [[REG2]], r2
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; CHECK-BE: cmp [[REG1]], r1
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; CHECK: movwls [[CARRY_HI]], #1
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; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
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; CHECK: cmp [[CARRY_HI]], #0
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; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]
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; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
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; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
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; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
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; CHECK: mov [[CMP:[a-z0-9]+]], #0
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; CHECK: movwhs [[CMP]], #1
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; CHECK: cmp [[CMP]], #0
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; CHECK: movne [[OUT_HI]], [[REG2]]
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; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
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; CHECK: movne [[OUT_LO]], [[REG1]]
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb {{ish$}}
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@ -322,21 +313,18 @@ define i64 @test11(i64* %ptr, i64 %val) {
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; CHECK-THUMB-LABEL: test11:
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; CHECK-THUMB: dmb {{ish$}}
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0
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; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0
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; CHECK-THUMB-LE: cmp [[REG1]], r2
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; CHECK-THUMB-BE: cmp [[REG2]], r3
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; CHECK-THUMB: movls.w [[CARRY_LO]], #1
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; CHECK-THUMB-LE: cmp [[REG2]], r3
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; CHECK-THUMB-BE: cmp [[REG1]], r2
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; CHECK-THUMB: movls [[CARRY_HI]], #1
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; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
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; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
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; CHECK-THUMB: cmp [[CARRY_HI]], #0
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; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
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; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
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; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]
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; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
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; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
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; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
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; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0
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; CHECK-THUMB: movhs.w [[CMP]], #1
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; CHECK-THUMB: cmp.w [[CMP]], #0
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; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
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; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
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; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb {{ish$}}
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@ -349,21 +337,18 @@ define i64 @test12(i64* %ptr, i64 %val) {
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; CHECK-LABEL: test12:
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; CHECK: dmb {{ish$}}
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
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; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
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; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
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; CHECK-LE: cmp [[REG1]], r1
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; CHECK-BE: cmp [[REG2]], r2
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; CHECK: movwhi [[CARRY_LO]], #1
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; CHECK-LE: cmp [[REG2]], r2
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; CHECK-BE: cmp [[REG1]], r1
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; CHECK: movwgt [[CARRY_HI]], #1
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; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
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; CHECK: cmp [[CARRY_HI]], #0
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; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]
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; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
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; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
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; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
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; CHECK: mov [[CMP:[a-z0-9]+]], #0
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; CHECK: movwlt [[CMP]], #1
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; CHECK: cmp [[CMP]], #0
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; CHECK: movne [[OUT_HI]], [[REG2]]
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; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
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; CHECK: movne [[OUT_LO]], [[REG1]]
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb {{ish$}}
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@ -371,21 +356,18 @@ define i64 @test12(i64* %ptr, i64 %val) {
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; CHECK-THUMB-LABEL: test12:
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; CHECK-THUMB: dmb {{ish$}}
|
||||
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
|
||||
; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0
|
||||
; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0
|
||||
; CHECK-THUMB-LE: cmp [[REG1]], r2
|
||||
; CHECK-THUMB-BE: cmp [[REG2]], r3
|
||||
; CHECK-THUMB: movhi.w [[CARRY_LO]], #1
|
||||
; CHECK-THUMB-LE: cmp [[REG2]], r3
|
||||
; CHECK-THUMB-BE: cmp [[REG1]], r2
|
||||
; CHECK-THUMB: movgt [[CARRY_HI]], #1
|
||||
; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
|
||||
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
|
||||
; CHECK-THUMB: cmp [[CARRY_HI]], #0
|
||||
; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
|
||||
; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
|
||||
; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]
|
||||
; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
|
||||
; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
|
||||
; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
|
||||
; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0
|
||||
; CHECK-THUMB: movlt.w [[CMP]], #1
|
||||
; CHECK-THUMB: cmp.w [[CMP]], #0
|
||||
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
|
||||
; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
|
||||
; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
|
||||
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
|
||||
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
|
||||
; CHECK-THUMB: cmp
|
||||
; CHECK-THUMB: bne
|
||||
; CHECK-THUMB: dmb {{ish$}}
|
||||
@ -398,21 +380,18 @@ define i64 @test13(i64* %ptr, i64 %val) {
|
||||
; CHECK-LABEL: test13:
|
||||
; CHECK: dmb {{ish$}}
|
||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||
; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
|
||||
; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
|
||||
; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
|
||||
; CHECK-LE: cmp [[REG1]], r1
|
||||
; CHECK-BE: cmp [[REG2]], r2
|
||||
; CHECK: movwhi [[CARRY_LO]], #1
|
||||
; CHECK-LE: cmp [[REG2]], r2
|
||||
; CHECK-BE: cmp [[REG1]], r1
|
||||
; CHECK: movwhi [[CARRY_HI]], #1
|
||||
; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
|
||||
; CHECK: cmp [[CARRY_HI]], #0
|
||||
; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]
|
||||
; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
|
||||
; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
|
||||
; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
|
||||
; CHECK: mov [[CMP:[a-z0-9]+]], #0
|
||||
; CHECK: movwlo [[CMP]], #1
|
||||
; CHECK: cmp [[CMP]], #0
|
||||
; CHECK: movne [[OUT_HI]], [[REG2]]
|
||||
; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
|
||||
; CHECK: movne [[OUT_LO]], [[REG1]]
|
||||
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
|
||||
; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb {{ish$}}
|
||||
@ -420,21 +399,18 @@ define i64 @test13(i64* %ptr, i64 %val) {
|
||||
; CHECK-THUMB-LABEL: test13:
|
||||
; CHECK-THUMB: dmb {{ish$}}
|
||||
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
|
||||
; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0
|
||||
; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0
|
||||
; CHECK-THUMB-LE: cmp [[REG1]], r2
|
||||
; CHECK-THUMB-BE: cmp [[REG2]], r3
|
||||
; CHECK-THUMB: movhi.w [[CARRY_LO]], #1
|
||||
; CHECK-THUMB-LE: cmp [[REG2]], r3
|
||||
; CHECK-THUMB-BE: cmp [[REG1]], r2
|
||||
; CHECK-THUMB: movhi [[CARRY_HI]], #1
|
||||
; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
|
||||
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
|
||||
; CHECK-THUMB: cmp [[CARRY_HI]], #0
|
||||
; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
|
||||
; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
|
||||
; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]
|
||||
; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
|
||||
; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
|
||||
; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
|
||||
; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0
|
||||
; CHECK-THUMB: movlo.w [[CMP]], #1
|
||||
; CHECK-THUMB: cmp.w [[CMP]], #0
|
||||
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
|
||||
; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
|
||||
; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
|
||||
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
|
||||
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
|
||||
; CHECK-THUMB: cmp
|
||||
; CHECK-THUMB: bne
|
||||
; CHECK-THUMB: dmb {{ish$}}
|
||||
|
||||
@ -667,19 +667,14 @@ define void @test_atomic_load_min_i64(i64 %offset) nounwind {
|
||||
; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
|
||||
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
|
||||
; function there.
|
||||
; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM-LE: cmp [[OLD1]], r0
|
||||
; CHECK-ARM-LE: movwls [[LOCARRY]], #1
|
||||
; CHECK-ARM-LE: cmp [[OLD2]], r1
|
||||
; CHECK-ARM-LE: movwle [[HICARRY]], #1
|
||||
; CHECK-ARM-BE: cmp [[OLD2]], r1
|
||||
; CHECK-ARM-BE: movwls [[LOCARRY]], #1
|
||||
; CHECK-ARM-BE: cmp [[OLD1]], r0
|
||||
; CHECK-ARM-BE: movwle [[HICARRY]], #1
|
||||
; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]]
|
||||
; CHECK-ARM: cmp [[HICARRY]], #0
|
||||
; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1
|
||||
; CHECK-ARM-LE: subs {{[^,]+}}, r0, [[OLD1]]
|
||||
; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]]
|
||||
; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]]
|
||||
; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]]
|
||||
; CHECK-ARM: mov [[CMP:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM: movwge [[CMP:r[0-9]+|lr]], #1
|
||||
; CHECK-ARM: cmp [[CMP:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM: movne [[MINHI]], [[OLD2]]
|
||||
; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0
|
||||
; CHECK-ARM: movne [[MINLO]], [[OLD1]]
|
||||
@ -785,19 +780,14 @@ define void @test_atomic_load_max_i64(i64 %offset) nounwind {
|
||||
; CHECK: ldrexd [[OLD1:r[0-9]+]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
|
||||
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
|
||||
; function there.
|
||||
; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM-LE: cmp [[OLD1]], r0
|
||||
; CHECK-ARM-LE: movwhi [[LOCARRY]], #1
|
||||
; CHECK-ARM-LE: cmp [[OLD2]], r1
|
||||
; CHECK-ARM-LE: movwgt [[HICARRY]], #1
|
||||
; CHECK-ARM-BE: cmp [[OLD2]], r1
|
||||
; CHECK-ARM-BE: movwhi [[LOCARRY]], #1
|
||||
; CHECK-ARM-BE: cmp [[OLD1]], r0
|
||||
; CHECK-ARM-BE: movwgt [[HICARRY]], #1
|
||||
; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]]
|
||||
; CHECK-ARM: cmp [[HICARRY]], #0
|
||||
; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1
|
||||
; CHECK-ARM-LE: subs {{[^,]+}}, r0, [[OLD1]]
|
||||
; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]]
|
||||
; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]]
|
||||
; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]]
|
||||
; CHECK-ARM: mov [[CMP:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM: movwlt [[CMP:r[0-9]+|lr]], #1
|
||||
; CHECK-ARM: cmp [[CMP:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM: movne [[MINHI]], [[OLD2]]
|
||||
; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0
|
||||
; CHECK-ARM: movne [[MINLO]], [[OLD1]]
|
||||
@ -903,19 +893,14 @@ define void @test_atomic_load_umin_i64(i64 %offset) nounwind {
|
||||
; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
|
||||
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
|
||||
; function there.
|
||||
; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM-LE: cmp [[OLD1]], r0
|
||||
; CHECK-ARM-LE: movwls [[LOCARRY]], #1
|
||||
; CHECK-ARM-LE: cmp [[OLD2]], r1
|
||||
; CHECK-ARM-LE: movwls [[HICARRY]], #1
|
||||
; CHECK-ARM-BE: cmp [[OLD2]], r1
|
||||
; CHECK-ARM-BE: movwls [[LOCARRY]], #1
|
||||
; CHECK-ARM-BE: cmp [[OLD1]], r0
|
||||
; CHECK-ARM-BE: movwls [[HICARRY]], #1
|
||||
; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]]
|
||||
; CHECK-ARM: cmp [[HICARRY]], #0
|
||||
; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1
|
||||
; CHECK-ARM-LE: subs {{[^,]+}}, r0, [[OLD1]]
|
||||
; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]]
|
||||
; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]]
|
||||
; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]]
|
||||
; CHECK-ARM: mov [[CMP:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM: movwhs [[CMP:r[0-9]+|lr]], #1
|
||||
; CHECK-ARM: cmp [[CMP:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM: movne [[MINHI]], [[OLD2]]
|
||||
; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0
|
||||
; CHECK-ARM: movne [[MINLO]], [[OLD1]]
|
||||
@ -1021,19 +1006,14 @@ define void @test_atomic_load_umax_i64(i64 %offset) nounwind {
|
||||
; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
|
||||
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
|
||||
; function there.
|
||||
; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM-LE: cmp [[OLD1]], r0
|
||||
; CHECK-ARM-LE: movwhi [[LOCARRY]], #1
|
||||
; CHECK-ARM-LE: cmp [[OLD2]], r1
|
||||
; CHECK-ARM-LE: movwhi [[HICARRY]], #1
|
||||
; CHECK-ARM-BE: cmp [[OLD2]], r1
|
||||
; CHECK-ARM-BE: movwhi [[LOCARRY]], #1
|
||||
; CHECK-ARM-BE: cmp [[OLD1]], r0
|
||||
; CHECK-ARM-BE: movwhi [[HICARRY]], #1
|
||||
; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]]
|
||||
; CHECK-ARM: cmp [[HICARRY]], #0
|
||||
; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1
|
||||
; CHECK-ARM-LE: subs {{[^,]+}}, r0, [[OLD1]]
|
||||
; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]]
|
||||
; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]]
|
||||
; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]]
|
||||
; CHECK-ARM: mov [[CMP:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM: movwlo [[CMP:r[0-9]+|lr]], #1
|
||||
; CHECK-ARM: cmp [[CMP:r[0-9]+|lr]], #0
|
||||
; CHECK-ARM: movne [[MINHI]], [[OLD2]]
|
||||
; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0
|
||||
; CHECK-ARM: movne [[MINLO]], [[OLD1]]
|
||||
|
||||
52
test/CodeGen/ARM/wide-compares.ll
Normal file
52
test/CodeGen/ARM/wide-compares.ll
Normal file
@ -0,0 +1,52 @@
|
||||
; RUN: llc -mtriple=armv7-unknown-linux < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ARM %s
|
||||
; RUN: llc -mtriple=thumbv6-unknown-linux < %s | FileCheck --check-prefix=CHECK-THUMB1 %s
|
||||
; RUN: llc -mtriple=thumbv7-unknown-linux < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-THUMB2 %s
|
||||
|
||||
; CHECK-THUMB1-NOT: sbc
|
||||
|
||||
; CHECK-LABEL: test_slt1:
|
||||
define i32 @test_slt1(i64 %a, i64 %b) {
|
||||
entry:
|
||||
; CHECK-ARM: subs {{[^,]+}}, r0, r2
|
||||
; CHECK-ARM: mov [[TMP:[0-9a-z]+]], #2
|
||||
; CHECK-ARM: sbcs {{[^,]+}}, r1, r3
|
||||
; CHECK-ARM: movwlt [[TMP]], #1
|
||||
; CHECK-ARM: mov r0, [[TMP]]
|
||||
; CHECK-ARM: bx lr
|
||||
; CHECK-THUMB2: subs {{[^,]+}}, r0, r2
|
||||
; CHECK-THUMB2: mov.w [[TMP:[0-9a-z]+]], #2
|
||||
; CHECK-THUMB2: sbcs.w {{[^,]+}}, r1, r3
|
||||
; CHECK-THUMB2: it lt
|
||||
; CHECK-THUMB2: movlt.w [[TMP]], #1
|
||||
; CHECK-THUMB2: mov r0, [[TMP]]
|
||||
; CHECK-THUMB2: bx lr
|
||||
%cmp = icmp slt i64 %a, %b
|
||||
br i1 %cmp, label %bb1, label %bb2
|
||||
bb1:
|
||||
ret i32 1
|
||||
bb2:
|
||||
ret i32 2
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_slt2:
|
||||
define void @test_slt2(i64 %a, i64 %b) {
|
||||
entry:
|
||||
%cmp = icmp slt i64 %a, %b
|
||||
; CHECK-ARM: subs {{[^,]+}}, r0, r2
|
||||
; CHECK-ARM: sbcs {{[^,]+}}, r1, r3
|
||||
; CHECK-THUMB2: subs {{[^,]+}}, r0, r2
|
||||
; CHECK-THUMB2: sbcs.w {{[^,]+}}, r1, r3
|
||||
; CHECK: bge [[BB2:\.[0-9A-Za-z_]+]]
|
||||
br i1 %cmp, label %bb1, label %bb2
|
||||
bb1:
|
||||
call void @f()
|
||||
ret void
|
||||
bb2:
|
||||
; CHECK: [[BB2]]:
|
||||
; CHECK-NEXT: bl g
|
||||
call void @g()
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @f()
|
||||
declare void @g()
|
||||
Loading…
x
Reference in New Issue
Block a user