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Change all #include'd files to be :: rules instead of : rules
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8019 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -48,7 +48,7 @@ TARGET_NAME := SparcV9
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TABLEGEN_FILES := $(wildcard *.td)
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$(TARGET_NAME)CodeEmitter.inc: $(TABLEGEN_FILES) $(TBLGEN)
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$(TARGET_NAME)CodeEmitter.inc:: $(TABLEGEN_FILES) $(TBLGEN)
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$(TBLGEN) $(TARGET_NAME).td -gen-emitter -o $@
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clean::
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@ -7,22 +7,22 @@ $(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
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X86GenRegisterInfo.inc X86GenInstrNames.inc \
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X86GenInstrInfo.inc X86GenInstrSelector.inc
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X86GenRegisterNames.inc: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
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X86GenRegisterNames.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
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$(TBLGEN) $< -gen-register-enums -o $@
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X86GenRegisterInfo.h.inc: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
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X86GenRegisterInfo.h.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
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$(TBLGEN) $< -gen-register-desc-header -o $@
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X86GenRegisterInfo.inc: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
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X86GenRegisterInfo.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
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$(TBLGEN) $< -gen-register-desc -o $@
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X86GenInstrNames.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
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X86GenInstrNames.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
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$(TBLGEN) $< -gen-instr-enums -o $@
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X86GenInstrInfo.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
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X86GenInstrInfo.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
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$(TBLGEN) $< -gen-instr-desc -o $@
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X86GenInstrSelector.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
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X86GenInstrSelector.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
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$(TBLGEN) $< -gen-instr-selector -o $@
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clean::
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