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[CodeGen] Rename AtomicRMWExpansionKind to AtomicExpansionKind.

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This lets us generalize its usage to the other atomic instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247428 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha 2015-09-11 17:08:17 +00:00
parent dee68c80b9
commit f3d2de3832
9 changed files with 24 additions and 26 deletions
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7
include/llvm/Target/TargetLowering.h
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@ -128,7 +128,7 @@ public:
/// because different targets have different levels of support for these
/// atomic RMW instructions, and also have different options w.r.t. what they
/// should expand to.
enum class AtomicRMWExpansionKind {
enum class AtomicExpansionKind {
None, // Don't expand the instruction.
LLSC, // Expand the instruction into loadlinked/storeconditional; used
// by ARM/AArch64. Implies `hasLoadLinkedStoreConditional`
@ -1120,9 +1120,8 @@ public:
/// Returns how the IR-level AtomicExpand pass should expand the given
/// AtomicRMW, if at all. Default is to never expand.
virtual AtomicRMWExpansionKind
shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
return AtomicRMWExpansionKind::None;
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
return AtomicExpansionKind::None;
}
/// On some platforms, an AtomicRMW that never actually modifies the value

6
lib/CodeGen/AtomicExpandPass.cpp
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@ -240,9 +240,9 @@ static void createCmpXchgInstFun(IRBuilder<> &Builder, Value *Addr,
bool AtomicExpand::tryExpandAtomicRMW(AtomicRMWInst *AI) {
switch (TLI->shouldExpandAtomicRMWInIR(AI)) {
case TargetLoweringBase::AtomicRMWExpansionKind::None:
case TargetLoweringBase::AtomicExpansionKind::None:
return false;
case TargetLoweringBase::AtomicRMWExpansionKind::LLSC: {
case TargetLoweringBase::AtomicExpansionKind::LLSC: {
assert(TLI->hasLoadLinkedStoreConditional() &&
"TargetLowering requested we expand AtomicRMW instruction into "
"load-linked/store-conditional combos, but such instructions aren't "
@ -250,7 +250,7 @@ bool AtomicExpand::tryExpandAtomicRMW(AtomicRMWInst *AI) {
return expandAtomicRMWToLLSC(AI);
}
case TargetLoweringBase::AtomicRMWExpansionKind::CmpXChg: {
case TargetLoweringBase::AtomicExpansionKind::CmpXChg: {
return expandAtomicRMWToCmpXchg(AI, createCmpXchgInstFun);
}
}

5
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -9498,11 +9498,10 @@ bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
}
// For the real atomic operations, we have ldxr/stxr up to 128 bits,
TargetLoweringBase::AtomicRMWExpansionKind
TargetLoweringBase::AtomicExpansionKind
AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
unsigned Size = AI->getType()->getPrimitiveSizeInBits();
return Size <= 128 ? AtomicRMWExpansionKind::LLSC
: AtomicRMWExpansionKind::None;
return Size <= 128 ? AtomicExpansionKind::LLSC : AtomicExpansionKind::None;
}
bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {

2
lib/Target/AArch64/AArch64ISelLowering.h
View File

@ -351,7 +351,7 @@ public:
bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
TargetLoweringBase::AtomicRMWExpansionKind
TargetLoweringBase::AtomicExpansionKind
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
bool useLoadStackGuardNode() const override;

6
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -11534,12 +11534,12 @@ bool ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
// For the real atomic operations, we have ldrex/strex up to 32 bits,
// and up to 64 bits on the non-M profiles
TargetLoweringBase::AtomicRMWExpansionKind
TargetLoweringBase::AtomicExpansionKind
ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
unsigned Size = AI->getType()->getPrimitiveSizeInBits();
return (Size <= (Subtarget->isMClass() ? 32U : 64U))
? AtomicRMWExpansionKind::LLSC
: AtomicRMWExpansionKind::None;
? AtomicExpansionKind::LLSC
: AtomicExpansionKind::None;
}
// This has so far only been implemented for MachO.

2
lib/Target/ARM/ARMISelLowering.h
View File

@ -438,7 +438,7 @@ namespace llvm {
bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
TargetLoweringBase::AtomicRMWExpansionKind
TargetLoweringBase::AtomicExpansionKind
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
bool useLoadStackGuardNode() const override;

6
lib/Target/Hexagon/HexagonISelLowering.h
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@ -218,9 +218,9 @@ bool isPositiveHalfWord(SDNode *N);
Value *Addr, AtomicOrdering Ord) const override;
bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
AtomicRMWExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI)
const override {
return AtomicRMWExpansionKind::LLSC;
AtomicExpansionKind
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
return AtomicExpansionKind::LLSC;
}
};
} // end namespace llvm

14
lib/Target/X86/X86ISelLowering.cpp
View File

@ -18411,7 +18411,7 @@ bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
return needsCmpXchgNb(PTy->getElementType());
}
TargetLoweringBase::AtomicRMWExpansionKind
TargetLoweringBase::AtomicExpansionKind
X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
Type *MemType = AI->getType();
@ -18419,8 +18419,8 @@ X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
// If the operand is too big, we must see if cmpxchg8/16b is available
// and default to library calls otherwise.
if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
: AtomicRMWExpansionKind::None;
return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
: AtomicExpansionKind::None;
}
AtomicRMWInst::BinOp Op = AI->getOperation();
@ -18431,14 +18431,14 @@ X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
case AtomicRMWInst::Add:
case AtomicRMWInst::Sub:
// It's better to use xadd, xsub or xchg for these in all cases.
return AtomicRMWExpansionKind::None;
return AtomicExpansionKind::None;
case AtomicRMWInst::Or:
case AtomicRMWInst::And:
case AtomicRMWInst::Xor:
// If the atomicrmw's result isn't actually used, we can just add a "lock"
// prefix to a normal instruction for these operations.
return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
: AtomicRMWExpansionKind::None;
return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
: AtomicExpansionKind::None;
case AtomicRMWInst::Nand:
case AtomicRMWInst::Max:
case AtomicRMWInst::Min:
@ -18446,7 +18446,7 @@ X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
case AtomicRMWInst::UMin:
// These always require a non-trivial set of data operations on x86. We must
// use a cmpxchg loop.
return AtomicRMWExpansionKind::CmpXChg;
return AtomicExpansionKind::CmpXChg;
}
}

2
lib/Target/X86/X86ISelLowering.h
View File

@ -1055,7 +1055,7 @@ namespace llvm {
bool shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
TargetLoweringBase::AtomicRMWExpansionKind
TargetLoweringBase::AtomicExpansionKind
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
LoadInst *