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Add a second vector type to the VRRC register class, and fix some patterns

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so that tablegen can infer all types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24746 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-12-16 09:19:13 +00:00
parent 0647bf6965
commit f492f9901a
2 changed files with 6 additions and 6 deletions
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6
lib/Target/PowerPC/PPCInstrInfo.td
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@ -946,11 +946,11 @@ def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
(srl GPRC:$rS, (sub 32, GPRC:$rB))), (srl GPRC:$rS, (sub 32, GPRC:$rB))),
(RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>; (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
def : Pat<(zext GPRC:$in), def : Pat<(i64 (zext GPRC:$in)),
(RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
def : Pat<(anyext GPRC:$in), def : Pat<(i64 (anyext GPRC:$in)),
(OR4To8 GPRC:$in, GPRC:$in)>; (OR4To8 GPRC:$in, GPRC:$in)>;
def : Pat<(trunc G8RC:$in), def : Pat<(i32 (trunc G8RC:$in)),
(OR8To4 G8RC:$in, G8RC:$in)>; (OR8To4 G8RC:$in, G8RC:$in)>;
// SHL // SHL

6
lib/Target/PowerPC/PPCRegisterInfo.td
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@ -191,9 +191,9 @@ def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>; F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
def VRRC : RegisterClass<"PPC", [v4f32], 128, [V0, V1, V2, V3, V4, V5, V6, V7, def VRRC : RegisterClass<"PPC", [v4f32,v4i32], 128, [V0, V1, V2, V3, V4, V5,
V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
V24, V25, V26, V27, V28, V29, V30, V31]>; V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>;
def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2,
CR3, CR4]>; CR3, CR4]>;