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Tidy up indentation. No functional change.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161727 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-08-11 17:53:00 +00:00
parent dca72541d5
commit f4cfc4423c
1 changed files with 25 additions and 25 deletions
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50
lib/Target/X86/X86FastISel.cpp
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@ -157,9 +157,9 @@ bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) {
// For now, require SSE/SSE2 for performing floating-point operations,
// since x87 requires additional work.
if (VT == MVT::f64 && !X86ScalarSSEf64)
return false;
return false;
if (VT == MVT::f32 && !X86ScalarSSEf32)
return false;
return false;
// Similarly, no f80 support yet.
if (VT == MVT::f80)
return false;
@ -1529,7 +1529,7 @@ static unsigned computeBytesPoppedByCallee(const X86Subtarget &Subtarget,
return 0;
if (!CS.paramHasAttr(1, Attribute::StructRet))
return 0;
if (CS.paramHasAttr(1, Attribute::InReg))
if (CS.paramHasAttr(1, Attribute::InReg))
return 0;
return 4;
}
@ -2142,28 +2142,28 @@ unsigned X86FastISel::TargetMaterializeFloatZero(const ConstantFP *CF) {
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
switch (VT.SimpleTy) {
default: return false;
case MVT::f32:
if (X86ScalarSSEf32) {
Opc = X86::FsFLD0SS;
RC = &X86::FR32RegClass;
} else {
Opc = X86::LD_Fp032;
RC = &X86::RFP32RegClass;
}
break;
case MVT::f64:
if (X86ScalarSSEf64) {
Opc = X86::FsFLD0SD;
RC = &X86::FR64RegClass;
} else {
Opc = X86::LD_Fp064;
RC = &X86::RFP64RegClass;
}
break;
case MVT::f80:
// No f80 support yet.
return false;
default: return false;
case MVT::f32:
if (X86ScalarSSEf32) {
Opc = X86::FsFLD0SS;
RC = &X86::FR32RegClass;
} else {
Opc = X86::LD_Fp032;
RC = &X86::RFP32RegClass;
}
break;
case MVT::f64:
if (X86ScalarSSEf64) {
Opc = X86::FsFLD0SD;
RC = &X86::FR64RegClass;
} else {
Opc = X86::LD_Fp064;
RC = &X86::RFP64RegClass;
}
break;
case MVT::f80:
// No f80 support yet.
return false;
}
unsigned ResultReg = createResultReg(RC);