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[AArch64] allow and-not-compare transform to form 'bics'

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This target hook was added with D19087:
https://reviews.llvm.org/D19087

Differential Revision: https://reviews.llvm.org/D27221


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288206 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2016-11-29 22:28:58 +00:00
parent 29916a15c8
commit f4d1201a27
2 changed files with 7 additions and 6 deletions
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5
lib/Target/AArch64/AArch64ISelLowering.h
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@ -412,6 +412,11 @@ public:
return true;
}
bool hasAndNotCompare(SDValue) const override {
// 'bics'
return true;
}
bool hasBitPreservingFPLogic(EVT VT) const override {
// FIXME: Is this always true? It should be true for vectors at least.
return VT == MVT::f32 || VT == MVT::f64;

8
test/CodeGen/AArch64/bics.ll
View File

@ -13,13 +13,10 @@ define i1 @andn_cmp(i32 %x, i32 %y) {
ret i1 %cmp
}
; FIXME: Recognize a disguised bics.
define i1 @and_cmp(i32 %x, i32 %y) {
; CHECK-LABEL: and_cmp:
; CHECK: // BB#0:
; CHECK-NEXT: and w8, w0, w1
; CHECK-NEXT: cmp w8, w1
; CHECK-NEXT: bics wzr, w1, w0
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
;
@ -32,8 +29,7 @@ define i1 @and_cmp_const(i32 %x) {
; CHECK-LABEL: and_cmp_const:
; CHECK: // BB#0:
; CHECK-NEXT: mov w8, #43
; CHECK-NEXT: and w8, w0, w8
; CHECK-NEXT: cmp w8, #43
; CHECK-NEXT: bics wzr, w8, w0
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
;