mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-14 23:48:49 +00:00
unify SelectExpr and SelectFP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22308 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
ba5dc44b00
commit
f4da945302
@ -566,7 +566,6 @@ public:
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
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unsigned SelectExpr(SDOperand N);
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unsigned SelectExprFP(SDOperand N, unsigned Result);
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void Select(SDOperand N);
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void SelectAddr(SDOperand N, unsigned& Reg, long& offset);
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@ -1081,184 +1080,6 @@ void AlphaISel::SelectBranchCC(SDOperand N)
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abort(); //Should never be reached
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}
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unsigned AlphaISel::SelectExprFP(SDOperand N, unsigned Result)
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{
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unsigned Tmp1, Tmp2, Tmp3;
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unsigned Opc = 0;
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SDNode *Node = N.Val;
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MVT::ValueType DestType = N.getValueType();
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unsigned opcode = N.getOpcode();
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switch (opcode) {
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default:
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Node->dump();
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assert(0 && "Node not handled!\n");
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case ISD::UNDEF: {
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BuildMI(BB, Alpha::IDEF, 0, Result);
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return Result;
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}
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case ISD::FNEG:
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if(ISD::FABS == N.getOperand(0).getOpcode())
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{
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
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} else {
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
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}
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return Result;
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case ISD::FABS:
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
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return Result;
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case ISD::SELECT:
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{
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//Tmp1 = SelectExpr(N.getOperand(0)); //Cond
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unsigned TV = SelectExpr(N.getOperand(1)); //Use if TRUE
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unsigned FV = SelectExpr(N.getOperand(2)); //Use if FALSE
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SDOperand CC = N.getOperand(0);
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SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
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if (CC.getOpcode() == ISD::SETCC &&
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!MVT::isInteger(SetCC->getOperand(0).getValueType()))
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{ //FP Setcc -> Select yay!
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//for a cmp b: c = a - b;
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//a = b: c = 0
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//a < b: c < 0
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//a > b: c > 0
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bool invTest = false;
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unsigned Tmp3;
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ConstantFPSDNode *CN;
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if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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Tmp3 = SelectExpr(SetCC->getOperand(0));
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else if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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{
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Tmp3 = SelectExpr(SetCC->getOperand(1));
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invTest = true;
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}
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else
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{
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unsigned Tmp1 = SelectExpr(SetCC->getOperand(0));
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unsigned Tmp2 = SelectExpr(SetCC->getOperand(1));
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bool isD = SetCC->getOperand(0).getValueType() == MVT::f64;
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Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
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BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
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.addReg(Tmp1).addReg(Tmp2);
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}
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switch (SetCC->getCondition()) {
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default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
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case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNE : Alpha::FCMOVEQ; break;
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case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGT : Alpha::FCMOVLT; break;
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case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGE : Alpha::FCMOVLE; break;
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case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLT : Alpha::FCMOVGT; break;
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case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLE : Alpha::FCMOVGE; break;
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case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQ : Alpha::FCMOVNE; break;
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}
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BuildMI(BB, Opc, 3, Result).addReg(FV).addReg(TV).addReg(Tmp3);
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return Result;
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}
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else
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{
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Tmp1 = SelectExpr(N.getOperand(0)); //Cond
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BuildMI(BB, Alpha::FCMOVEQ_INT, 3, Result).addReg(TV).addReg(FV)
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.addReg(Tmp1);
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// // Spill the cond to memory and reload it from there.
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// unsigned Tmp4 = MakeReg(MVT::f64);
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// MoveIntFP(Tmp1, Tmp4, true);
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// //now ideally, we don't have to do anything to the flag...
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// // Get the condition into the zero flag.
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// BuildMI(BB, Alpha::FCMOVEQ, 3, Result).addReg(TV).addReg(FV).addReg(Tmp4);
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return Result;
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}
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}
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case ISD::FP_ROUND:
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assert (DestType == MVT::f32 &&
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N.getOperand(0).getValueType() == MVT::f64 &&
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"only f64 to f32 conversion supported here");
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Tmp1);
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return Result;
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case ISD::FP_EXTEND:
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assert (DestType == MVT::f64 &&
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N.getOperand(0).getValueType() == MVT::f32 &&
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"only f32 to f64 conversion supported here");
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
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return Result;
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case ISD::ConstantFP:
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if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
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if (CN->isExactlyValue(+0.0)) {
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BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31)
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.addReg(Alpha::F31);
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} else if ( CN->isExactlyValue(-0.0)) {
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BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31)
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.addReg(Alpha::F31);
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} else {
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abort();
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}
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}
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return Result;
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case ISD::SDIV:
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case ISD::MUL:
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case ISD::ADD:
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case ISD::SUB:
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switch( opcode ) {
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case ISD::MUL: Opc = DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS;
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break;
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case ISD::ADD: Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS;
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break;
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case ISD::SUB: Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS;
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break;
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case ISD::SDIV: Opc = DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS;
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break;
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};
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ConstantFPSDNode *CN;
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if (opcode == ISD::SUB
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&& (CN = dyn_cast<ConstantFPSDNode>(N.getOperand(0)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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{
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp2).addReg(Tmp2);
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} else {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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return Result;
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case ISD::SINT_TO_FP:
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{
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assert (N.getOperand(0).getValueType() == MVT::i64
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&& "only quads can be loaded from");
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Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
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Tmp2 = MakeReg(MVT::f64);
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MoveInt2FP(Tmp1, Tmp2, true);
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Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
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BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
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return Result;
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}
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}
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assert(0 && "should not get here");
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return 0;
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}
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unsigned AlphaISel::SelectExpr(SDOperand N) {
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unsigned Result;
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unsigned Tmp1, Tmp2 = 0, Tmp3;
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@ -1267,6 +1088,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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SDNode *Node = N.Val;
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MVT::ValueType DestType = N.getValueType();
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bool isFP = DestType == MVT::f64 || DestType == MVT::f32;
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unsigned &Reg = ExprMap[N];
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if (Reg) return Reg;
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@ -1288,11 +1110,6 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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}
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}
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if ((DestType == MVT::f64 || DestType == MVT::f32)
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&& opcode != ISD::CALL && opcode != ISD::TAILCALL
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&& opcode != ISD::CopyFromReg && opcode != ISD::LOAD)
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return SelectExprFP(N, Result);
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switch (opcode) {
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default:
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Node->dump();
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@ -1800,7 +1617,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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Select(Chain);
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unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
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//std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
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if (DestType == MVT::f32 || DestType == MVT::f64)
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if (isFP)
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BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
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else
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BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);
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@ -1876,7 +1693,6 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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case ISD::SRL:
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case ISD::SRA:
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case ISD::MUL:
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assert (DestType == MVT::i64 && "Only do arithmetic on i64s!");
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if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
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{
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@ -1900,7 +1716,10 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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case ISD::SHL: Opc = Alpha::SL; break;
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case ISD::SRL: Opc = Alpha::SRL; break;
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case ISD::SRA: Opc = Alpha::SRA; break;
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case ISD::MUL: Opc = Alpha::MULQ; break;
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case ISD::MUL:
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Opc = isFP ? (DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS)
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: Alpha::MULQ;
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break;
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};
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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@ -1910,7 +1729,25 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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case ISD::ADD:
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case ISD::SUB:
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{
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if (isFP) {
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ConstantFPSDNode *CN;
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if (opcode == ISD::ADD)
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Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS;
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else
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Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS;
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if (opcode == ISD::SUB
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&& (CN = dyn_cast<ConstantFPSDNode>(N.getOperand(0)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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{
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp2).addReg(Tmp2);
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} else {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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return Result;
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} else {
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bool isAdd = opcode == ISD::ADD;
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//first check for Scaled Adds and Subs!
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@ -1977,7 +1814,12 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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}
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case ISD::SDIV:
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{
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if (isFP) {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS, 2, Result)
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.addReg(Tmp1).addReg(Tmp2);
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} else {
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ConstantSDNode* CSD;
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//check if we can convert into a shift!
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if ((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1).Val)) &&
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@ -2070,7 +1912,73 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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}
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case ISD::SELECT:
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{
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if (isFP) {
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//Tmp1 = SelectExpr(N.getOperand(0)); //Cond
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unsigned TV = SelectExpr(N.getOperand(1)); //Use if TRUE
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unsigned FV = SelectExpr(N.getOperand(2)); //Use if FALSE
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SDOperand CC = N.getOperand(0);
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SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
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if (CC.getOpcode() == ISD::SETCC &&
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!MVT::isInteger(SetCC->getOperand(0).getValueType()))
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{ //FP Setcc -> Select yay!
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//for a cmp b: c = a - b;
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//a = b: c = 0
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//a < b: c < 0
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//a > b: c > 0
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bool invTest = false;
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unsigned Tmp3;
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ConstantFPSDNode *CN;
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if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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Tmp3 = SelectExpr(SetCC->getOperand(0));
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else if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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{
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Tmp3 = SelectExpr(SetCC->getOperand(1));
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invTest = true;
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}
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else
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{
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unsigned Tmp1 = SelectExpr(SetCC->getOperand(0));
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unsigned Tmp2 = SelectExpr(SetCC->getOperand(1));
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bool isD = SetCC->getOperand(0).getValueType() == MVT::f64;
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Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
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BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
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.addReg(Tmp1).addReg(Tmp2);
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}
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switch (SetCC->getCondition()) {
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default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
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case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNE : Alpha::FCMOVEQ; break;
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case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGT : Alpha::FCMOVLT; break;
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case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGE : Alpha::FCMOVLE; break;
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case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLT : Alpha::FCMOVGT; break;
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case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLE : Alpha::FCMOVGE; break;
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case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQ : Alpha::FCMOVNE; break;
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}
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BuildMI(BB, Opc, 3, Result).addReg(FV).addReg(TV).addReg(Tmp3);
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return Result;
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}
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else
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{
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Tmp1 = SelectExpr(N.getOperand(0)); //Cond
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BuildMI(BB, Alpha::FCMOVEQ_INT, 3, Result).addReg(TV).addReg(FV)
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.addReg(Tmp1);
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// // Spill the cond to memory and reload it from there.
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// unsigned Tmp4 = MakeReg(MVT::f64);
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// MoveIntFP(Tmp1, Tmp4, true);
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// //now ideally, we don't have to do anything to the flag...
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// // Get the condition into the zero flag.
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// BuildMI(BB, Alpha::FCMOVEQ, 3, Result).addReg(TV).addReg(FV).addReg(Tmp4);
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return Result;
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}
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} else {
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//FIXME: look at parent to decide if intCC can be folded, or if setCC(FP)
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//and can save stack use
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//Tmp1 = SelectExpr(N.getOperand(0)); //Cond
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@ -2176,6 +2084,63 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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}
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return Result;
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}
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case ISD::FNEG:
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if(ISD::FABS == N.getOperand(0).getOpcode())
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{
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
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} else {
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
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}
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return Result;
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case ISD::FABS:
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
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return Result;
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case ISD::FP_ROUND:
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assert (DestType == MVT::f32 &&
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N.getOperand(0).getValueType() == MVT::f64 &&
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"only f64 to f32 conversion supported here");
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Tmp1);
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return Result;
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case ISD::FP_EXTEND:
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assert (DestType == MVT::f64 &&
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N.getOperand(0).getValueType() == MVT::f32 &&
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"only f32 to f64 conversion supported here");
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
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return Result;
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case ISD::ConstantFP:
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if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
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if (CN->isExactlyValue(+0.0)) {
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BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31)
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.addReg(Alpha::F31);
|
||||
} else if ( CN->isExactlyValue(-0.0)) {
|
||||
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31)
|
||||
.addReg(Alpha::F31);
|
||||
} else {
|
||||
abort();
|
||||
}
|
||||
}
|
||||
return Result;
|
||||
|
||||
case ISD::SINT_TO_FP:
|
||||
{
|
||||
assert (N.getOperand(0).getValueType() == MVT::i64
|
||||
&& "only quads can be loaded from");
|
||||
Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
|
||||
Tmp2 = MakeReg(MVT::f64);
|
||||
MoveInt2FP(Tmp1, Tmp2, true);
|
||||
Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
|
||||
BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
|
||||
return Result;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user