RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-27 13:40:30 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[AArch64] Generate literals by the little end

Browse Source 
ARM seems to prefer that long literals be formed from their little end in
order to promote the fusion of the instrs pairs MOV/MOVK and MOVK/MOVK on
Cortex A57 and others (v.  "Cortex A57 Software Optimisation Guide", section
4.14).

Differential revision: https://reviews.llvm.org/D28697

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292422 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evandro Menezes 2017-01-18 18:57:08 +00:00
parent d20f95e583
commit f5697dce74
21 changed files with 135 additions and 135 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
View File

@ -539,15 +539,15 @@ bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
if (Imm != 0) {
unsigned LZ = countLeadingZeros(Imm);
unsigned TZ = countTrailingZeros(Imm);
Shift = ((63 - LZ) / 16) * 16;
LastShift = (TZ / 16) * 16;
Shift = (TZ / 16) * 16;
LastShift = ((63 - LZ) / 16) * 16;
}
unsigned Imm16 = (Imm >> Shift) & Mask;
bool DstIsDead = MI.getOperand(0).isDead();
MachineInstrBuilder MIB1 =
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(FirstOpc))
.addReg(DstReg, RegState::Define |
getDeadRegState(DstIsDead && Shift == LastShift))
getDeadRegState(DstIsDead && Shift == LastShift))
.addImm(Imm16)
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift));
@ -564,15 +564,15 @@ bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
MachineInstrBuilder MIB2;
unsigned Opc = (BitSize == 32 ? AArch64::MOVKWi : AArch64::MOVKXi);
while (Shift != LastShift) {
Shift -= 16;
while (Shift < LastShift) {
Shift += 16;
Imm16 = (Imm >> Shift) & Mask;
if (Imm16 == (isNeg ? Mask : 0))
continue; // This 16-bit portion is already set correctly.
MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
.addReg(DstReg,
RegState::Define |
getDeadRegState(DstIsDead && Shift == LastShift))
getDeadRegState(DstIsDead && Shift == LastShift))
.addReg(DstReg)
.addImm(Imm16)
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift));

10
lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -1299,16 +1299,16 @@ bool AArch64InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
.addMemOperand(*MI.memoperands_begin());
} else if (TM.getCodeModel() == CodeModel::Large) {
BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg)
.addGlobalAddress(GV, 0, AArch64II::MO_G3).addImm(48);
BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
.addReg(Reg, RegState::Kill)
.addGlobalAddress(GV, 0, AArch64II::MO_G2 | MO_NC).addImm(32);
.addGlobalAddress(GV, 0, AArch64II::MO_G0 | MO_NC).addImm(0);
BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
.addReg(Reg, RegState::Kill)
.addGlobalAddress(GV, 0, AArch64II::MO_G1 | MO_NC).addImm(16);
BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
.addReg(Reg, RegState::Kill)
.addGlobalAddress(GV, 0, AArch64II::MO_G0 | MO_NC).addImm(0);
.addGlobalAddress(GV, 0, AArch64II::MO_G2 | MO_NC).addImm(32);
BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
.addReg(Reg, RegState::Kill)
.addGlobalAddress(GV, 0, AArch64II::MO_G3).addImm(48);
BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
.addReg(Reg, RegState::Kill)
.addImm(0)

32
lib/Target/AArch64/AArch64InstrInfo.td
View File

@ -576,31 +576,31 @@ def : Pat<(f64 fpimm:$in),
// sequences.
def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
tglobaladdr:$g1, tglobaladdr:$g0),
(MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
tglobaladdr:$g2, 32),
tglobaladdr:$g1, 16),
tglobaladdr:$g0, 0)>;
(MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g0, 0),
tglobaladdr:$g1, 16),
tglobaladdr:$g2, 32),
tglobaladdr:$g3, 48)>;
def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
tblockaddress:$g1, tblockaddress:$g0),
(MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
tblockaddress:$g2, 32),
tblockaddress:$g1, 16),
tblockaddress:$g0, 0)>;
(MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g0, 0),
tblockaddress:$g1, 16),
tblockaddress:$g2, 32),
tblockaddress:$g3, 48)>;
def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
tconstpool:$g1, tconstpool:$g0),
(MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
tconstpool:$g2, 32),
tconstpool:$g1, 16),
tconstpool:$g0, 0)>;
(MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g0, 0),
tconstpool:$g1, 16),
tconstpool:$g2, 32),
tconstpool:$g3, 48)>;
def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
tjumptable:$g1, tjumptable:$g0),
(MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
tjumptable:$g2, 32),
tjumptable:$g1, 16),
tjumptable:$g0, 0)>;
(MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g0, 0),
tjumptable:$g1, 16),
tjumptable:$g2, 32),
tjumptable:$g3, 48)>;
//===----------------------------------------------------------------------===//

4
test/CodeGen/AArch64/arm64-addrmode.ll
View File

@ -112,8 +112,8 @@ define void @t10(i64 %a) {
define void @t11(i64 %a) {
; CHECK-LABEL: t11:
; CHECK: mov w[[NUM:[0-9]+]], #19070976
; CHECK: movk w[[NUM:[0-9]+]], #17767
; CHECK: mov w[[NUM:[0-9]+]], #17767
; CHECK: movk w[[NUM:[0-9]+]], #291
; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]]
%1 = add i64 %a, 19088743 ;0x1234567
%2 = inttoptr i64 %1 to i64*

8
test/CodeGen/AArch64/arm64-bitfield-extract.ll
View File

@ -348,8 +348,8 @@ entry:
; CHECK-LABEL: fct16:
; CHECK: ldr [[REG1:w[0-9]+]],
; Create the constant
; CHECK: mov [[REGCST:w[0-9]+]], #1703936
; CHECK: movk [[REGCST]], #33120
; CHECK: mov [[REGCST:w[0-9]+]], #33120
; CHECK: movk [[REGCST]], #26, lsl #16
; Do the masking
; CHECK: and [[REG2:w[0-9]+]], [[REG1]], [[REGCST]]
; CHECK-NEXT: bfxil [[REG2]], w1, #16, #3
@ -377,8 +377,8 @@ entry:
; CHECK-LABEL: fct17:
; CHECK: ldr [[REG1:x[0-9]+]],
; Create the constant
; CHECK: mov w[[REGCST:[0-9]+]], #1703936
; CHECK: movk w[[REGCST]], #33120
; CHECK: mov w[[REGCST:[0-9]+]], #33120
; CHECK: movk w[[REGCST]], #26, lsl #16
; Do the masking
; CHECK: and [[REG2:x[0-9]+]], [[REG1]], x[[REGCST]]
; CHECK-NEXT: bfxil [[REG2]], x1, #16, #3

6
test/CodeGen/AArch64/arm64-blockaddress.ll
View File

@ -15,10 +15,10 @@ entry:
; CHECK-LINUX: add {{x[0-9]+}}, [[REG]], :lo12:.Ltmp1
; CHECK-LARGE-LABEL: t:
; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g3:[[DEST_LBL:.Ltmp[0-9]+]]
; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g0_nc:[[DEST_LBL:.Ltmp[0-9]+]]
; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g1_nc:[[DEST_LBL]]
; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g0_nc:[[DEST_LBL]]
; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g3:[[DEST_LBL]]
%recover = alloca i64, align 8
store volatile i64 ptrtoint (i8* blockaddress(@t, %mylabel) to i64), i64* %recover, align 8

36
test/CodeGen/AArch64/arm64-code-model-large-abs.ll
View File

@ -9,10 +9,10 @@ define i8* @global_addr() {
; CHECK-LABEL: global_addr:
ret i8* @var8
; The movz/movk calculation should end up returned directly in x0.
; CHECK: movz x0, #:abs_g3:var8
; CHECK: movk x0, #:abs_g2_nc:var8
; CHECK: movz x0, #:abs_g0_nc:var8
; CHECK: movk x0, #:abs_g1_nc:var8
; CHECK: movk x0, #:abs_g0_nc:var8
; CHECK: movk x0, #:abs_g2_nc:var8
; CHECK: movk x0, #:abs_g3:var8
; CHECK-NEXT: ret
}
@ -20,10 +20,10 @@ define i8 @global_i8() {
; CHECK-LABEL: global_i8:
%val = load i8, i8* @var8
ret i8 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var8
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
; CHECK: movk x[[ADDR_REG]], #:abs_g3:var8
; CHECK: ldrb w0, [x[[ADDR_REG]]]
}
@ -31,10 +31,10 @@ define i16 @global_i16() {
; CHECK-LABEL: global_i16:
%val = load i16, i16* @var16
ret i16 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var16
; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var16
; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var16
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
; CHECK: movk x[[ADDR_REG]], #:abs_g3:var16
; CHECK: ldrh w0, [x[[ADDR_REG]]]
}
@ -42,10 +42,10 @@ define i32 @global_i32() {
; CHECK-LABEL: global_i32:
%val = load i32, i32* @var32
ret i32 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var32
; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var32
; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var32
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
; CHECK: movk x[[ADDR_REG]], #:abs_g3:var32
; CHECK: ldr w0, [x[[ADDR_REG]]]
}
@ -53,10 +53,10 @@ define i64 @global_i64() {
; CHECK-LABEL: global_i64:
%val = load i64, i64* @var64
ret i64 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var64
; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var64
; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var64
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
; CHECK: movk x[[ADDR_REG]], #:abs_g3:var64
; CHECK: ldr x0, [x[[ADDR_REG]]]
}
@ -64,9 +64,9 @@ define <2 x i64> @constpool() {
; CHECK-LABEL: constpool:
ret <2 x i64> <i64 123456789, i64 987654321100>
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:[[CPADDR:.LCPI[0-9]+_[0-9]+]]
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:[[CPADDR]]
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:[[CPADDR:.LCPI[0-9]+_[0-9]+]]
; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:[[CPADDR]]
; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:[[CPADDR]]
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:[[CPADDR]]
; CHECK: movk x[[ADDR_REG]], #:abs_g3:[[CPADDR]]
; CHECK: ldr q0, [x[[ADDR_REG]]]
}

4
test/CodeGen/AArch64/arm64-const-addr.ll
View File

@ -5,8 +5,8 @@
; Test if the constant base address gets only materialized once.
define i32 @test1() nounwind {
; CHECK-LABEL: test1
; CHECK: mov w8, #68091904
; CHECK-NEXT: movk w8, #49152
; CHECK: mov w8, #49152
; CHECK-NEXT: movk w8, #1039, lsl #16
; CHECK-NEXT: ldp w9, w10, [x8, #4]
; CHECK: ldr w8, [x8, #12]
%at = inttoptr i64 68141056 to %T*

18
test/CodeGen/AArch64/arm64-extern-weak.ll
View File

@ -15,10 +15,10 @@ define i32()* @foo() {
; In the large model, the usual relocations are absolute and can
; materialise 0.
; CHECK-LARGE: movz x0, #:abs_g3:var
; CHECK-LARGE: movk x0, #:abs_g2_nc:var
; CHECK-LARGE: movz x0, #:abs_g0_nc:var
; CHECK-LARGE: movk x0, #:abs_g1_nc:var
; CHECK-LARGE: movk x0, #:abs_g0_nc:var
; CHECK-LARGE: movk x0, #:abs_g2_nc:var
; CHECK-LARGE: movk x0, #:abs_g3:var
}
@ -33,10 +33,10 @@ define i32* @bar() {
; In the large model, the usual relocations are absolute and can
; materialise 0.
; CHECK-LARGE: movz [[ARR_VAR:x[0-9]+]], #:abs_g3:arr_var
; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g2_nc:arr_var
; CHECK-LARGE: movz [[ARR_VAR:x[0-9]+]], #:abs_g0_nc:arr_var
; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g1_nc:arr_var
; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g0_nc:arr_var
; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g2_nc:arr_var
; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g3:arr_var
}
@defined_weak_var = internal unnamed_addr global i32 0
@ -46,8 +46,8 @@ define i32* @wibble() {
; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var
; CHECK: add x0, [[BASE]], :lo12:defined_weak_var
; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var
; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
; CHECK-LARGE: movz x0, #:abs_g0_nc:defined_weak_var
; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var
; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var
; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
; CHECK-LARGE: movk x0, #:abs_g3:defined_weak_var
}

4
test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll
View File

@ -37,9 +37,9 @@ entry:
define signext i8 @foo3() nounwind ssp {
entry:
; CHECK-LABEL: @foo3
; CHECK: mov x[[REG:[0-9]+]], #12343736008704
; CHECK: mov x[[REG:[0-9]+]], #12274
; CHECK: movk x[[REG]], #29646, lsl #16
; CHECK: movk x[[REG]], #12274
; CHECK: movk x[[REG]], #2874, lsl #32
%0 = load i8*, i8** @pd2, align 8
%arrayidx = getelementptr inbounds i8, i8* %0, i64 12345678901234
%1 = load i8, i8* %arrayidx, align 1

22
test/CodeGen/AArch64/arm64-movi.ll
View File

@ -51,24 +51,24 @@ define i32 @movz() nounwind {
define i64 @movz_3movk() nounwind {
; CHECK-LABEL: movz_3movk:
; CHECK: mov x0, #1407374883553280
; CHECK-NEXT: movk x0, #4660, lsl #32
; CHECK: mov x0, #22136
; CHECK-NEXT: movk x0, #43981, lsl #16
; CHECK-NEXT: movk x0, #22136
; CHECK-NEXT: movk x0, #4660, lsl #32
; CHECK-NEXT: movk x0, #5, lsl #48
ret i64 1427392313513592
}
define i64 @movz_movk_skip1() nounwind {
; CHECK-LABEL: movz_movk_skip1:
; CHECK: mov x0, #21474836480
; CHECK-NEXT: movk x0, #17185, lsl #16
; CHECK: mov x0, #1126236160
; CHECK-NEXT: movk x0, #5, lsl #32
ret i64 22601072640
}
define i64 @movz_skip1_movk() nounwind {
; CHECK-LABEL: movz_skip1_movk:
; CHECK: mov x0, #147695335374848
; CHECK-NEXT: movk x0, #4660
; CHECK: mov x0, #4660
; CHECK-NEXT: movk x0, #34388, lsl #32
ret i64 147695335379508
}
@ -84,8 +84,8 @@ define i64 @movn() nounwind {
define i64 @movn_skip1_movk() nounwind {
; CHECK-LABEL: movn_skip1_movk:
; CHECK: mov x0, #-176093659137
; CHECK-NEXT: movk x0, #4660
; CHECK: mov x0, #-60876
; CHECK-NEXT: movk x0, #65494, lsl #32
ret i64 -176093720012
}
@ -195,8 +195,8 @@ define i64 @orr_movk13() nounwind {
; rdar://13944082
define i64 @g() nounwind {
; CHECK-LABEL: g:
; CHECK: mov x0, #-281474976710656
; CHECK: movk x0, #2
; CHECK: mov x0, #2
; CHECK: movk x0, #65535, lsl #48
entry:
ret i64 -281474976710654
}

12
test/CodeGen/AArch64/bitfield-insert.ll
View File

@ -428,8 +428,8 @@ define i32 @test5(i32 %a) {
; BFXIL will use the same constant as the ORR, so we don't care how the constant
; is materialized (it's an equal cost either way).
; CHECK-LABEL: @test6
; CHECK: mov [[REG:w[0-9]+]], #720896
; CHECK: movk [[REG]], #23250
; CHECK: mov [[REG:w[0-9]+]], #23250
; CHECK: movk [[REG]], #11, lsl #16
; CHECK: bfxil w0, [[REG]], #0, #20
define i32 @test6(i32 %a) {
%1 = and i32 %a, 4293918720 ; 0xfff00000
@ -440,8 +440,8 @@ define i32 @test6(i32 %a) {
; BFIs that require the same number of instruction to materialize the constant
; as the original ORR are okay.
; CHECK-LABEL: @test7
; CHECK: mov [[REG:w[0-9]+]], #327680
; CHECK: movk [[REG]], #44393
; CHECK: mov [[REG:w[0-9]+]], #44393
; CHECK: movk [[REG]], #5, lsl #16
; CHECK: bfi w0, [[REG]], #1, #19
define i32 @test7(i32 %a) {
%1 = and i32 %a, 4293918721 ; 0xfff00001
@ -454,9 +454,9 @@ define i32 @test7(i32 %a) {
; 'and' with a 'movk', which would decrease ILP while using the same number of
; instructions.
; CHECK-LABEL: @test8
; CHECK: mov [[REG2:x[0-9]+]], #157599529959424
; CHECK: mov [[REG2:x[0-9]+]], #2035482624
; CHECK: and [[REG1:x[0-9]+]], x0, #0xff000000000000ff
; CHECK: movk [[REG2]], #31059, lsl #16
; CHECK: movk [[REG2]], #36694, lsl #32
; CHECK: orr x0, [[REG1]], [[REG2]]
define i64 @test8(i64 %a) {
%1 = and i64 %a, -72057594037927681 ; 0xff000000000000ff

6
test/CodeGen/AArch64/blockaddress.ll
View File

@ -14,10 +14,10 @@ define void @test_blockaddress() {
; CHECK: ldr [[NEWDEST:x[0-9]+]]
; CHECK: br [[NEWDEST]]
; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g3:[[DEST_LBL:.Ltmp[0-9]+]]
; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g0_nc:[[DEST_LBL:.Ltmp[0-9]+]]
; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g1_nc:[[DEST_LBL]]
; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g0_nc:[[DEST_LBL]]
; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g3:[[DEST_LBL]]
; CHECK-LARGE: str [[ADDR_REG]],
; CHECK-LARGE: ldr [[NEWDEST:x[0-9]+]]
; CHECK-LARGE: br [[NEWDEST]]

30
test/CodeGen/AArch64/code-model-large-abs.ll
View File

@ -9,10 +9,10 @@ define i8* @global_addr() {
; CHECK-LABEL: global_addr:
ret i8* @var8
; The movz/movk calculation should end up returned directly in x0.
; CHECK: movz x0, #:abs_g3:var8
; CHECK: movk x0, #:abs_g2_nc:var8
; CHECK: movz x0, #:abs_g0_nc:var8
; CHECK: movk x0, #:abs_g1_nc:var8
; CHECK: movk x0, #:abs_g0_nc:var8
; CHECK: movk x0, #:abs_g2_nc:var8
; CHECK: movk x0, #:abs_g3:var8
; CHECK-NEXT: ret
}
@ -20,10 +20,10 @@ define i8 @global_i8() {
; CHECK-LABEL: global_i8:
%val = load i8, i8* @var8
ret i8 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var8
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
; CHECK: movk x[[ADDR_REG]], #:abs_g3:var8
; CHECK: ldrb w0, [x[[ADDR_REG]]]
}
@ -31,10 +31,10 @@ define i16 @global_i16() {
; CHECK-LABEL: global_i16:
%val = load i16, i16* @var16
ret i16 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var16
; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var16
; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var16
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
; CHECK: movk x[[ADDR_REG]], #:abs_g3:var16
; CHECK: ldrh w0, [x[[ADDR_REG]]]
}
@ -42,10 +42,10 @@ define i32 @global_i32() {
; CHECK-LABEL: global_i32:
%val = load i32, i32* @var32
ret i32 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var32
; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var32
; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var32
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
; CHECK: movk x[[ADDR_REG]], #:abs_g3:var32
; CHECK: ldr w0, [x[[ADDR_REG]]]
}
@ -53,9 +53,9 @@ define i64 @global_i64() {
; CHECK-LABEL: global_i64:
%val = load i64, i64* @var64
ret i64 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var64
; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var64
; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var64
; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
; CHECK: movk x[[ADDR_REG]], #:abs_g3:var64
; CHECK: ldr x0, [x[[ADDR_REG]]]
}

18
test/CodeGen/AArch64/extern-weak.ll
View File

@ -16,10 +16,10 @@ define i32()* @foo() {
; In the large model, the usual relocations are absolute and can
; materialise 0.
; CHECK-LARGE: movz x0, #:abs_g3:var
; CHECK-LARGE: movk x0, #:abs_g2_nc:var
; CHECK-LARGE: movz x0, #:abs_g0_nc:var
; CHECK-LARGE: movk x0, #:abs_g1_nc:var
; CHECK-LARGE: movk x0, #:abs_g0_nc:var
; CHECK-LARGE: movk x0, #:abs_g2_nc:var
; CHECK-LARGE: movk x0, #:abs_g3:var
}
@ -37,10 +37,10 @@ define i32* @bar() {
; In the large model, the usual relocations are absolute and can
; materialise 0.
; CHECK-LARGE: movz [[ADDR:x[0-9]+]], #:abs_g3:arr_var
; CHECK-LARGE: movk [[ADDR]], #:abs_g2_nc:arr_var
; CHECK-LARGE: movz [[ADDR:x[0-9]+]], #:abs_g0_nc:arr_var
; CHECK-LARGE: movk [[ADDR]], #:abs_g1_nc:arr_var
; CHECK-LARGE: movk [[ADDR]], #:abs_g0_nc:arr_var
; CHECK-LARGE: movk [[ADDR]], #:abs_g2_nc:arr_var
; CHECK-LARGE: movk [[ADDR]], #:abs_g3:arr_var
}
@defined_weak_var = internal unnamed_addr global i32 0
@ -51,8 +51,8 @@ define i32* @wibble() {
; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var
; CHECK: add x0, [[BASE]], :lo12:defined_weak_var
; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var
; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
; CHECK-LARGE: movz x0, #:abs_g0_nc:defined_weak_var
; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var
; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var
; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
; CHECK-LARGE: movk x0, #:abs_g3:defined_weak_var
}

10
test/CodeGen/AArch64/fpimm.ll
View File

@ -38,18 +38,18 @@ define void @check_double() {
}
; LARGE-LABEL: check_float2
; LARGE: mov [[REG:w[0-9]+]], #1078525952
; LARGE-NEXT: movk [[REG]], #4059
; LARGE: mov [[REG:w[0-9]+]], #4059
; LARGE-NEXT: movk [[REG]], #16457, lsl #16
; LARGE-NEXT: fmov s0, [[REG]]
define float @check_float2() {
ret float 3.14159274101257324218750
}
; LARGE-LABEL: check_double2
; LARGE: mov [[REG:x[0-9]+]], #4614219293217783808
; LARGE-NEXT: movk [[REG]], #8699, lsl #32
; LARGE: mov [[REG:x[0-9]+]], #11544
; LARGE-NEXT: movk [[REG]], #21572, lsl #16
; LARGE-NEXT: movk [[REG]], #11544
; LARGE-NEXT: movk [[REG]], #8699, lsl #32
; LARGE-NEXT: movk [[REG]], #16393, lsl #48
; LARGE-NEXT: fmov d0, [[REG]]
define double @check_double2() {
ret double 3.1415926535897931159979634685441851615905761718750

6
test/CodeGen/AArch64/jump-table.ll
View File

@ -16,10 +16,10 @@ define i32 @test_jumptable(i32 %in) {
; CHECK: ldr [[DEST:x[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #3]
; CHECK: br [[DEST]]
; CHECK-LARGE: movz x[[JTADDR:[0-9]+]], #:abs_g3:.LJTI0_0
; CHECK-LARGE: movk x[[JTADDR]], #:abs_g2_nc:.LJTI0_0
; CHECK-LARGE: movz x[[JTADDR:[0-9]+]], #:abs_g0_nc:.LJTI0_0
; CHECK-LARGE: movk x[[JTADDR]], #:abs_g1_nc:.LJTI0_0
; CHECK-LARGE: movk x[[JTADDR]], #:abs_g0_nc:.LJTI0_0
; CHECK-LARGE: movk x[[JTADDR]], #:abs_g2_nc:.LJTI0_0
; CHECK-LARGE: movk x[[JTADDR]], #:abs_g3:.LJTI0_0
; CHECK-LARGE: ldr [[DEST:x[0-9]+]], [x[[JTADDR]], {{x[0-9]+}}, lsl #3]
; CHECK-LARGE: br [[DEST]]

6
test/CodeGen/AArch64/large-consts.ll
View File

@ -5,10 +5,10 @@
define double @foo() {
; CHECK: movz [[CPADDR:x[0-9]+]], #:abs_g3:.LCPI0_0 // encoding: [0bAAA01000,A,0b111AAAAA,0xd2]
; CHECK: movk [[CPADDR]], #:abs_g2_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b110AAAAA,0xf2]
; CHECK: movz [[CPADDR:x[0-9]+]], #:abs_g0_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b100AAAAA,0xd2]
; CHECK: movk [[CPADDR]], #:abs_g1_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b101AAAAA,0xf2]
; CHECK: movk [[CPADDR]], #:abs_g0_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b100AAAAA,0xf2]
; CHECK: movk [[CPADDR]], #:abs_g2_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b110AAAAA,0xf2]
; CHECK: movk [[CPADDR]], #:abs_g3:.LCPI0_0 // encoding: [0bAAA01000,A,0b111AAAAA,0xf2]
ret double 3.14159
}

12
test/CodeGen/AArch64/literal_pools_float.ll
View File

@ -15,10 +15,10 @@ define void @floating_lits() {
; CHECK: ldr [[LIT128:s[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
; CHECK-NOFP-NOT: ldr {{s[0-9]+}},
; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g0_nc:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]]
; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]]
; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
; CHECK-LARGE: movk x[[LITADDR]], #:abs_g3:[[CURLIT]]
; CHECK-LARGE: ldr {{s[0-9]+}}, [x[[LITADDR]]]
; CHECK-LARGE: fadd
; CHECK-NOFP-LARGE-NOT: ldr {{s[0-9]+}},
@ -33,10 +33,10 @@ define void @floating_lits() {
; CHECK-NOFP-NOT: ldr {{d[0-9]+}},
; CHECK-NOFP-NOT: fadd
; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g0_nc:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]]
; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]]
; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
; CHECK-LARGE: movk x[[LITADDR]], #:abs_g3:[[CURLIT]]
; CHECK-LARGE: ldr {{d[0-9]+}}, [x[[LITADDR]]]
; CHECK-NOFP-LARGE-NOT: ldr {{d[0-9]+}},

8
test/CodeGen/AArch64/movw-shift-encoding.ll
View File

@ -8,8 +8,8 @@
define i32* @get_var() {
ret i32* @var
; CHECK: movz x0, #:abs_g3:var // encoding: [0bAAA00000,A,0b111AAAAA,0xd2]
; CHECK: movk x0, #:abs_g2_nc:var // encoding: [0bAAA00000,A,0b110AAAAA,0xf2]
; CHECK: movk x0, #:abs_g1_nc:var // encoding: [0bAAA00000,A,0b101AAAAA,0xf2]
; CHECK: movk x0, #:abs_g0_nc:var // encoding: [0bAAA00000,A,0b100AAAAA,0xf2]
; CHECK: movz x0, #:abs_g0_nc:var // encoding: [0bAAA00000,A,0b100AAAAA,0xd2]
; CHECK: movk x0, #:abs_g1_nc:var // encoding: [0bAAA00000,A,0b101AAAAA,0xf2]
; CHECK: movk x0, #:abs_g2_nc:var // encoding: [0bAAA00000,A,0b110AAAAA,0xf2]
; CHECK: movk x0, #:abs_g3:var // encoding: [0bAAA00000,A,0b111AAAAA,0xf2]
}

6
test/CodeGen/AArch64/stack_guard_remat.ll
View File

@ -15,10 +15,10 @@
; PIC-LINUX: ldr {{x[0-9]+}}, {{\[}}[[R1]]{{\]}}
; STATIC-LARGE: foo2
; STATIC-LARGE: movz [[R0:x[0-9]+]], #:abs_g3:__stack_chk_guard
; STATIC-LARGE: movk [[R0]], #:abs_g2_nc:__stack_chk_guard
; STATIC-LARGE: movz [[R0:x[0-9]+]], #:abs_g0_nc:__stack_chk_guard
; STATIC-LARGE: movk [[R0]], #:abs_g1_nc:__stack_chk_guard
; STATIC-LARGE: movk [[R0]], #:abs_g0_nc:__stack_chk_guard
; STATIC-LARGE: movk [[R0]], #:abs_g2_nc:__stack_chk_guard
; STATIC-LARGE: movk [[R0]], #:abs_g3:__stack_chk_guard
; STATIC-LARGE: ldr {{x[0-9]+}}, {{\[}}[[R0]]{{\]}}
; STATIC-SMALL: foo2