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Fix a dagcombine to not generate loads of non-round integer types,

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as its comment says, even in the case where it will be generating
extending loads. This fixes PR3216.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62557 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-01-20 01:06:45 +00:00
parent c2997f4a34
commit f5add58549
2 changed files with 15 additions and 1 deletions
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2
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -3343,7 +3343,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
// Do not generate loads of non-round integer types since these can
// be expensive (and would be wrong if the type is not byte sized).
if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() &&
if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() &&
cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
// Do not change the width of a volatile load.
!cast<LoadSDNode>(N0)->isVolatile()) {

14
test/CodeGen/X86/pr3216.ll Normal file
View File

@ -0,0 +1,14 @@
; RUN: llvm-as < %s | llc -march=x86 | grep {sar. \$5}
@foo = global i8 127
define i32 @main() nounwind {
entry:
%tmp = load i8* @foo
%bf.lo = lshr i8 %tmp, 5
%bf.lo.cleared = and i8 %bf.lo, 7
%0 = shl i8 %bf.lo.cleared, 5
%bf.val.sext = ashr i8 %0, 5
%conv = sext i8 %bf.val.sext to i32
ret i32 %conv
}