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Delete the old spilling framework from LiveIntervalAnalysis.
This is dead code, all register allocators use InlineSpiller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144478 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
5d9b109181
commit
f5eeaf221c
@ -125,19 +125,6 @@ namespace llvm {
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return (unsigned)(IntervalPercentage * indexes_->getFunctionSize());
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}
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/// conflictsWithPhysReg - Returns true if the specified register is used or
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/// defined during the duration of the specified interval. Copies to and
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/// from li.reg are allowed. This method is only able to analyze simple
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/// ranges that stay within a single basic block. Anything else is
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/// considered a conflict.
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bool conflictsWithPhysReg(const LiveInterval &li, VirtRegMap &vrm,
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unsigned reg);
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/// conflictsWithAliasRef - Similar to conflictsWithPhysRegRef except
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/// it checks for alias uses and defs.
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bool conflictsWithAliasRef(LiveInterval &li, unsigned Reg,
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SmallPtrSet<MachineInstr*,32> &JoinedCopies);
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// Interval creation
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LiveInterval &getOrCreateInterval(unsigned reg) {
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Reg2IntervalMap::iterator I = r2iMap_.find(reg);
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@ -271,20 +258,6 @@ namespace llvm {
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/// print - Implement the dump method.
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virtual void print(raw_ostream &O, const Module* = 0) const;
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/// addIntervalsForSpills - Create new intervals for spilled defs / uses of
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/// the given interval. FIXME: It also returns the weight of the spill slot
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/// (if any is created) by reference. This is temporary.
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std::vector<LiveInterval*>
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addIntervalsForSpills(const LiveInterval& i,
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const SmallVectorImpl<LiveInterval*> *SpillIs,
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const MachineLoopInfo *loopInfo, VirtRegMap& vrm);
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/// spillPhysRegAroundRegDefsUses - Spill the specified physical register
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/// around all defs and uses of the specified interval. Return true if it
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/// was able to cut its interval.
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bool spillPhysRegAroundRegDefsUses(const LiveInterval &li,
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unsigned PhysReg, VirtRegMap &vrm);
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/// isReMaterializable - Returns true if every definition of MI of every
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/// val# of the specified interval is re-materializable. Also returns true
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/// by reference if all of the defs are load instructions.
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@ -292,20 +265,6 @@ namespace llvm {
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const SmallVectorImpl<LiveInterval*> *SpillIs,
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bool &isLoad);
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/// isReMaterializable - Returns true if the definition MI of the specified
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/// val# of the specified interval is re-materializable.
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bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
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MachineInstr *MI);
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/// getRepresentativeReg - Find the largest super register of the specified
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/// physical register.
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unsigned getRepresentativeReg(unsigned Reg) const;
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/// getNumConflictsWithPhysReg - Return the number of uses and defs of the
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/// specified interval that conflicts with the specified physical register.
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unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
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unsigned PhysReg) const;
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/// intervalIsInOneMBB - Returns true if the specified interval is entirely
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/// within a single basic block.
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bool intervalIsInOneMBB(const LiveInterval &li) const;
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@ -379,84 +338,6 @@ namespace llvm {
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const SmallVectorImpl<LiveInterval*> *SpillIs,
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bool &isLoad);
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/// tryFoldMemoryOperand - Attempts to fold either a spill / restore from
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/// slot / to reg or any rematerialized load into ith operand of specified
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/// MI. If it is successul, MI is updated with the newly created MI and
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/// returns true.
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bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
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MachineInstr *DefMI, SlotIndex InstrIdx,
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SmallVector<unsigned, 2> &Ops,
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bool isSS, int FrameIndex, unsigned Reg);
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/// canFoldMemoryOperand - Return true if the specified load / store
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/// folding is possible.
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bool canFoldMemoryOperand(MachineInstr *MI,
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SmallVector<unsigned, 2> &Ops,
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bool ReMatLoadSS) const;
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/// anyKillInMBBAfterIdx - Returns true if there is a kill of the specified
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/// VNInfo that's after the specified index but is within the basic block.
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bool anyKillInMBBAfterIdx(const LiveInterval &li, const VNInfo *VNI,
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MachineBasicBlock *MBB,
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SlotIndex Idx) const;
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/// hasAllocatableSuperReg - Return true if the specified physical register
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/// has any super register that's allocatable.
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bool hasAllocatableSuperReg(unsigned Reg) const;
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/// SRInfo - Spill / restore info.
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struct SRInfo {
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SlotIndex index;
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unsigned vreg;
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bool canFold;
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SRInfo(SlotIndex i, unsigned vr, bool f)
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: index(i), vreg(vr), canFold(f) {}
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};
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bool alsoFoldARestore(int Id, SlotIndex index, unsigned vr,
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BitVector &RestoreMBBs,
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DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
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void eraseRestoreInfo(int Id, SlotIndex index, unsigned vr,
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BitVector &RestoreMBBs,
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DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
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/// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
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/// spilled and create empty intervals for their uses.
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void handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
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const TargetRegisterClass* rc,
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std::vector<LiveInterval*> &NewLIs);
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/// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
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/// interval on to-be re-materialized operands of MI) with new register.
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void rewriteImplicitOps(const LiveInterval &li,
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MachineInstr *MI, unsigned NewVReg, VirtRegMap &vrm);
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/// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper
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/// functions for addIntervalsForSpills to rewrite uses / defs for the given
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/// live range.
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bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
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bool TrySplit, SlotIndex index, SlotIndex end,
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MachineInstr *MI, MachineInstr *OrigDefMI, MachineInstr *DefMI,
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unsigned Slot, int LdSlot,
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bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
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VirtRegMap &vrm, const TargetRegisterClass* rc,
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SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
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unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
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DenseMap<unsigned,unsigned> &MBBVRegsMap,
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std::vector<LiveInterval*> &NewLIs);
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void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
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LiveInterval::Ranges::const_iterator &I,
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MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
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bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
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VirtRegMap &vrm, const TargetRegisterClass* rc,
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SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
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BitVector &SpillMBBs,
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DenseMap<unsigned,std::vector<SRInfo> > &SpillIdxes,
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BitVector &RestoreMBBs,
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DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes,
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DenseMap<unsigned,unsigned> &MBBVRegsMap,
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std::vector<LiveInterval*> &NewLIs);
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static LiveInterval* createInterval(unsigned Reg);
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void printInstrs(raw_ostream &O) const;
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