diff --git a/test/CodeGen/PowerPC/andc.ll b/test/CodeGen/PowerPC/andc.ll
index 6135db510ad..f9b1e4876fd 100644
--- a/test/CodeGen/PowerPC/andc.ll
+++ b/test/CodeGen/PowerPC/andc.ll
@@ -1,12 +1,13 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s
 
 define i1 @and_cmp1(i32 %x, i32 %y) {
 ; CHECK-LABEL: and_cmp1:
-; CHECK: andc [[REG1:r[0-9]+]], r4, r3
-; CHECK: cntlzw   [[REG2:r[0-9]+]], [[REG1]]
-; CHECK: rlwinm r3, [[REG2]], 27, 31, 31
-; CHECK: blr
-
+; CHECK:       # BB#0:
+; CHECK-NEXT:    andc 3, 4, 3
+; CHECK-NEXT:    cntlzw 3, 3
+; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT:    blr
   %and = and i32 %x, %y
   %cmp = icmp eq i32 %and, %y
   ret i1 %cmp
@@ -14,12 +15,12 @@ define i1 @and_cmp1(i32 %x, i32 %y) {
 
 define i1 @and_cmp_const(i32 %x) {
 ; CHECK-LABEL: and_cmp_const:
-; CHECK: li [[REG1:r[0-9]+]], 43
-; CHECK: andc [[REG2:r[0-9]+]], [[REG1]], r3
-; CHECK: cntlzw   [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: rlwinm r3, [[REG3]], 27, 31, 31
-; CHECK: blr
-
+; CHECK:       # BB#0:
+; CHECK-NEXT:    li 4, 43
+; CHECK-NEXT:    andc 3, 4, 3
+; CHECK-NEXT:    cntlzw 3, 3
+; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT:    blr
   %and = and i32 %x, 43
   %cmp = icmp eq i32 %and, 43
   ret i1 %cmp
@@ -27,15 +28,28 @@ define i1 @and_cmp_const(i32 %x) {
 
 define i1 @foo(i32 %i) {
 ; CHECK-LABEL: foo:
-; CHECK: lis [[REG1:r[0-9]+]], 4660
-; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 22136
-; CHECK: andc [[REG3:r[0-9]+]], [[REG2]], r3
-; CHECK: cntlzw  [[REG4:r[0-9]+]], [[REG3]]
-; CHECK: rlwinm r3, [[REG4]], 27, 31, 31
-; CHECK: blr
-
+; CHECK:       # BB#0:
+; CHECK-NEXT:    lis 4, 4660
+; CHECK-NEXT:    ori 4, 4, 22136
+; CHECK-NEXT:    andc 3, 4, 3
+; CHECK-NEXT:    cntlzw 3, 3
+; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT:    blr
   %and = and i32 %i, 305419896
   %cmp = icmp eq i32 %and, 305419896
   ret i1 %cmp
 }
 
+define <4 x i32> @hidden_not_v4i32(<4 x i32> %x) {
+; CHECK-LABEL: hidden_not_v4i32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vspltisw 3, 15
+; CHECK-NEXT:    vspltisw 4, 6
+; CHECK-NEXT:    xxlxor 0, 34, 35
+; CHECK-NEXT:    xxland 34, 0, 36
+; CHECK-NEXT:    blr
+  %xor = xor <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>
+  %and = and <4 x i32> %xor, <i32 6, i32 6, i32 6, i32 6>
+  ret <4 x i32> %and
+}
+