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Disable the pattern isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15787 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -15,8 +15,7 @@ TARGET = X86
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# Make sure that tblgen is run, first thing.
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$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
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X86GenRegisterInfo.inc X86GenInstrNames.inc \
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X86GenInstrInfo.inc X86GenAsmWriter.inc \
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X86GenInstrSelector.inc
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X86GenInstrInfo.inc X86GenAsmWriter.inc
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TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \
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$(SourceDir)/../Target.td
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@ -45,9 +44,9 @@ $(TARGET)GenAsmWriter.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td assembly writer with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -o $@
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$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td instruction selector with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
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#$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
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# @echo "Building $(TARGET).td instruction selector with tblgen"
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# $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
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clean::
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$(VERB) rm -f *.inc
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@ -29,12 +29,6 @@ class IntrinsicLowering;
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///
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FunctionPass *createX86SimpleInstructionSelector(TargetMachine &TM);
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/// createX86PatternInstructionSelector - This pass converts an LLVM function
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/// into a machine code representation using pattern matching and a machine
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/// description file.
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///
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FunctionPass *createX86PatternInstructionSelector(TargetMachine &TM);
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/// createX86SSAPeepholeOptimizerPass - Create a pass to perform SSA-based X86
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/// specific peephole optimizations.
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///
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@ -14,6 +14,11 @@
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//
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//===----------------------------------------------------------------------===//
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/// NOTE: This whole selector is completely disabled. This is only retained
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/// for historical interest and future work. It will probably change
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/// substantially in the future.
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#if 0
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#include "X86.h"
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#include "llvm/Pass.h"
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#include "llvm/Function.h"
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@ -122,3 +127,5 @@ void ISel::expandCall(SelectionDAG &SD, CallInst &CI) {
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FunctionPass *llvm::createX86PatternInstructionSelector(TargetMachine &TM) {
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return new ISel(TM);
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}
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#endif
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@ -26,12 +26,6 @@
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using namespace llvm;
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namespace {
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#if 0 // FIXME: This will be used in the future.
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cl::opt<bool> NoPatternISel("disable-pattern-isel", cl::init(true),
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cl::desc("Use the 'simple' X86 instruction selector"));
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#else
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static const bool NoPatternISel = true;
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#endif
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cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
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cl::desc("Disable the ssa-based peephole optimizer "
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"(defaults to disabled)"));
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@ -87,10 +81,7 @@ bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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if (NoPatternISel)
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PM.add(createX86SimpleInstructionSelector(*this));
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else
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PM.add(createX86PatternInstructionSelector(*this));
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PM.add(createX86SimpleInstructionSelector(*this));
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// Run optional SSA-based machine code optimizations next...
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if (!NoSSAPeephole)
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@ -145,10 +136,7 @@ void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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if (NoPatternISel)
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PM.add(createX86SimpleInstructionSelector(TM));
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else
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PM.add(createX86PatternInstructionSelector(TM));
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PM.add(createX86SimpleInstructionSelector(TM));
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// Run optional SSA-based machine code optimizations next...
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if (!NoSSAPeephole)
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