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Update to new-style flags usage, simplifying the .td file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26106 91177308-0d34-0410-b5e6-96231b3b80d8
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Chris Lattner
parent
c57e5c17bc
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f613fcb741
@ -91,13 +91,11 @@ let PrintMethod = "printCCOperand" in
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def CCOp : Operand<i32>;
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def SDTSPcmpfcc :
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SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
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SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
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def SDTSPbrcc :
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SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
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SDTCisVT<2, FlagVT>]>;
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SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
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def SDTSPselectcc :
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SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
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SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>;
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SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
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def SDTSPFTOI :
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SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
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def SDTSPITOF :
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@ -105,8 +103,8 @@ SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
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def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
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def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>;
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def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain]>;
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def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain]>;
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def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
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def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
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def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
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def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
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@ -114,8 +112,8 @@ def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
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def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
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def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
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def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc>;
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def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc>;
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def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>;
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def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>;
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// These are target-independent nodes, but have target-specific formats.
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def SDT_SPCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
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@ -213,32 +211,32 @@ let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_ICC PSEUDO!",
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[(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
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imm:$Cond, ICC))]>;
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imm:$Cond))]>;
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def SELECT_CC_Int_FCC
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_FCC PSEUDO!",
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[(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
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imm:$Cond, FCC))]>;
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imm:$Cond))]>;
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def SELECT_CC_FP_ICC
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: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_FP_ICC PSEUDO!",
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[(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
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imm:$Cond, ICC))]>;
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imm:$Cond))]>;
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def SELECT_CC_FP_FCC
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: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_FP_FCC PSEUDO!",
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[(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F,
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imm:$Cond, FCC))]>;
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imm:$Cond))]>;
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def SELECT_CC_DFP_ICC
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: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_DFP_ICC PSEUDO!",
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[(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
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imm:$Cond, ICC))]>;
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imm:$Cond))]>;
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def SELECT_CC_DFP_FCC
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: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_DFP_FCC PSEUDO!",
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[(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F,
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imm:$Cond, FCC))]>;
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imm:$Cond))]>;
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}
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@ -605,7 +603,7 @@ let isBarrier = 1 in
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// FIXME: the encoding for the JIT should look at the condition field.
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def BCOND : BranchSP<0, (ops brtarget:$dst, CCOp:$cc),
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"b$cc $dst",
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[(SPbricc bb:$dst, imm:$cc, ICC)]>;
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[(SPbricc bb:$dst, imm:$cc)]>;
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// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
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@ -622,7 +620,7 @@ class FPBranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
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// FIXME: the encoding for the JIT should look at the condition field.
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def FBCOND : FPBranchSP<0, (ops brtarget:$dst, CCOp:$cc),
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"fb$cc $dst",
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[(SPbrfcc bb:$dst, imm:$cc, FCC)]>;
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[(SPbrfcc bb:$dst, imm:$cc)]>;
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// Section B.24 - Call and Link Instruction, p. 125
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@ -767,11 +765,11 @@ def FDIVD : F3_3<2, 0b110100, 0b001001110,
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def FCMPS : F3_3<2, 0b110101, 0b001010001,
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(ops FPRegs:$src1, FPRegs:$src2),
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"fcmps $src1, $src2\n\tnop",
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[(set FCC, (SPcmpfcc FPRegs:$src1, FPRegs:$src2))]>;
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[(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>;
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def FCMPD : F3_3<2, 0b110101, 0b001010010,
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(ops DFPRegs:$src1, DFPRegs:$src2),
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"fcmpd $src1, $src2\n\tnop",
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[(set FCC, (SPcmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
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[(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>;
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//===----------------------------------------------------------------------===//
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@ -786,44 +784,44 @@ let Predicates = [HasV9], isTwoAddress = 1 in {
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
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"mov$cc %icc, $F, $dst",
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[(set IntRegs:$dst,
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(SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc, ICC))]>;
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(SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
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def MOVICCri
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
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"mov$cc %icc, $F, $dst",
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[(set IntRegs:$dst,
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(SPselecticc simm11:$F, IntRegs:$T, imm:$cc, ICC))]>;
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(SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>;
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def MOVFCCrr
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
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"mov$cc %fcc0, $F, $dst",
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[(set IntRegs:$dst,
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(SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc, FCC))]>;
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(SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
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def MOVFCCri
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
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"mov$cc %fcc0, $F, $dst",
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[(set IntRegs:$dst,
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(SPselectfcc simm11:$F, IntRegs:$T, imm:$cc, FCC))]>;
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(SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>;
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def FMOVS_ICC
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: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
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"fmovs$cc %icc, $F, $dst",
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[(set FPRegs:$dst,
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(SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc, ICC))]>;
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(SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
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def FMOVD_ICC
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: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
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"fmovd$cc %icc, $F, $dst",
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[(set DFPRegs:$dst,
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(SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc, ICC))]>;
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(SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
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def FMOVS_FCC
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: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
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"fmovs$cc %fcc0, $F, $dst",
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[(set FPRegs:$dst,
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(SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc, FCC))]>;
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(SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
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def FMOVD_FCC
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: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
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"fmovd$cc %fcc0, $F, $dst",
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[(set DFPRegs:$dst,
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(SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc, FCC))]>;
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(SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
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}
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@ -68,15 +68,6 @@ def D10 : Rd<20, "F20", [F20, F21]>; def D11 : Rd<22, "F22", [F22, F23]>;
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def D12 : Rd<24, "F24", [F24, F25]>; def D13 : Rd<26, "F26", [F26, F27]>;
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def D14 : Rd<28, "F28", [F28, F29]>; def D15 : Rd<30, "F30", [F30, F31]>;
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/// Integer and FP Condition codes.
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let Namespace = "SP" in {
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def ICC : Register<"ICC">;
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def FCC : Register<"FCC">;
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}
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def FLAGS_REGS : RegisterClass<"SP", [FlagVT], 32, [ICC, FCC]> {
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let Size = 32;
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}
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// Register classes.
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//
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// FIXME: the register order should be defined in terms of the preferred
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