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[X86] Use implicit masking of SHLD/SHRD shift double instructions

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Similar to the regular shift instructions, SHLD/SHRD only use the bottom bits of the shift value


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277341 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim 2016-08-01 12:11:43 +00:00
parent ec511c29a7
commit f6cf26bc83
2 changed files with 20 additions and 16 deletions
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19
lib/Target/X86/X86InstrCompiler.td
View File

@ -1709,6 +1709,22 @@ defm : MaskedShiftAmountPats<sra, "SAR">;
defm : MaskedShiftAmountPats<rotl, "ROL">;
defm : MaskedShiftAmountPats<rotr, "ROR">;
// Double shift amount is implicitly masked.
multiclass MaskedDoubleShiftAmountPats<SDNode frag, string name> {
// (shift x (and y, 31)) ==> (shift x, y)
def : Pat<(frag GR16:$src1, GR16:$src2, (and CL, immShift32)),
(!cast<Instruction>(name # "16rrCL") GR16:$src1, GR16:$src2)>;
def : Pat<(frag GR32:$src1, GR32:$src2, (and CL, immShift32)),
(!cast<Instruction>(name # "32rrCL") GR32:$src1, GR32:$src2)>;
// (shift x (and y, 63)) ==> (shift x, y)
def : Pat<(frag GR64:$src1, GR64:$src2, (and CL, immShift64)),
(!cast<Instruction>(name # "64rrCL") GR64:$src1, GR64:$src2)>;
}
defm : MaskedDoubleShiftAmountPats<X86shld, "SHLD">;
defm : MaskedDoubleShiftAmountPats<X86shrd, "SHRD">;
// (anyext (setcc_carry)) -> (setcc_carry)
def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
(SETB_C16r)>;
@ -1717,9 +1733,6 @@ def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
(SETB_C32r)>;
//===----------------------------------------------------------------------===//
// EFLAGS-defining Patterns
//===----------------------------------------------------------------------===//

17
test/CodeGen/X86/shift-double.ll
View File

@ -156,7 +156,6 @@ define i64 @test8(i64 %val, i32 %bits) nounwind {
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: shll %cl, %eax
; CHECK-NEXT: andb $31, %cl
; CHECK-NEXT: shldl %cl, %esi, %edx
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
@ -169,15 +168,11 @@ define i64 @test8(i64 %val, i32 %bits) nounwind {
define i64 @test9(i64 %val, i32 %bits) nounwind {
; CHECK-LABEL: test9:
; CHECK: # BB#0:
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl %esi, %edx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: shrdl %cl, %edx, %eax
; CHECK-NEXT: sarl %cl, %edx
; CHECK-NEXT: andb $31, %cl
; CHECK-NEXT: shrdl %cl, %esi, %eax
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
%and = and i32 %bits, 31
%sh_prom = zext i32 %and to i64
@ -188,15 +183,11 @@ define i64 @test9(i64 %val, i32 %bits) nounwind {
define i64 @test10(i64 %val, i32 %bits) nounwind {
; CHECK-LABEL: test10:
; CHECK: # BB#0:
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl %esi, %edx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: shrdl %cl, %edx, %eax
; CHECK-NEXT: shrl %cl, %edx
; CHECK-NEXT: andb $31, %cl
; CHECK-NEXT: shrdl %cl, %esi, %eax
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
%and = and i32 %bits, 31
%sh_prom = zext i32 %and to i64