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Force the greedy register allocator to always use the inline spiller.
Soon, RegAllocGreedy will start splitting live ranges, and then deferred spilling won't work anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121591 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -311,7 +311,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
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getAnalysis<LiveIntervals>());
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getAnalysis<LiveIntervals>());
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ReservedRegs = TRI->getReservedRegs(*MF);
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ReservedRegs = TRI->getReservedRegs(*MF);
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SpillerInstance.reset(createSpiller(*this, *MF, *VRM));
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SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
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allocatePhysRegs();
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allocatePhysRegs();
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addMBBLiveIns(MF);
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addMBBLiveIns(MF);
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@ -231,12 +231,6 @@ public:
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} // end anonymous namespace
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} // end anonymous namespace
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namespace llvm {
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Spiller *createInlineSpiller(MachineFunctionPass &pass,
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MachineFunction &mf,
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VirtRegMap &vrm);
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}
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llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass,
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llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass,
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MachineFunction &mf,
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MachineFunction &mf,
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VirtRegMap &vrm) {
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VirtRegMap &vrm) {
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@ -44,6 +44,13 @@ namespace llvm {
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Spiller* createSpiller(MachineFunctionPass &pass,
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Spiller* createSpiller(MachineFunctionPass &pass,
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MachineFunction &mf,
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MachineFunction &mf,
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VirtRegMap &vrm);
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VirtRegMap &vrm);
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/// Create and return a spiller that will insert spill code directly instead
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/// of deferring though VirtRegMap.
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Spiller *createInlineSpiller(MachineFunctionPass &pass,
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MachineFunction &mf,
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VirtRegMap &vrm);
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}
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}
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#endif
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#endif
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