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[InstCombine] allow (icmp sgt smin(PosA, B), 0) fold for vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281624 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1376,11 +1376,10 @@ static Instruction *ProcessUGT_ADDCST_ADD(ICmpInst &I, Value *A, Value *B,
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// Fold icmp Pred X, C.
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Instruction *InstCombiner::foldICmpWithConstant(ICmpInst &Cmp) {
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CmpInst::Predicate Pred = Cmp.getPredicate();
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Value *X = Cmp.getOperand(0), *C = Cmp.getOperand(1);
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Value *X = Cmp.getOperand(0);
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// FIXME: Use m_APInt to allow folds for splat constants.
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ConstantInt *CI = dyn_cast<ConstantInt>(C);
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if (!CI)
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const APInt *C;
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if (!match(Cmp.getOperand(1), m_APInt(C)))
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return nullptr;
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Value *A = nullptr, *B = nullptr;
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@ -1400,21 +1399,26 @@ Instruction *InstCombiner::foldICmpWithConstant(ICmpInst &Cmp) {
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ConstantInt *CI2; // I = icmp ugt (add (add A, B), CI2), CI
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if (Pred == ICmpInst::ICMP_UGT &&
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match(X, m_Add(m_Add(m_Value(A), m_Value(B)), m_ConstantInt(CI2))))
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if (Instruction *Res = ProcessUGT_ADDCST_ADD(Cmp, A, B, CI2, CI, *this))
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if (Instruction *Res = ProcessUGT_ADDCST_ADD(
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Cmp, A, B, CI2, cast<ConstantInt>(Cmp.getOperand(1)), *this))
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return Res;
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}
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// (icmp sgt smin(PosA, B) 0) -> (icmp sgt B 0)
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if (CI->isZero() && Pred == ICmpInst::ICMP_SGT)
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if (auto *SI = dyn_cast<SelectInst>(X)) {
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SelectPatternResult SPR = matchSelectPattern(SI, A, B);
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if (SPR.Flavor == SPF_SMIN) {
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if (isKnownPositive(A, DL))
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return new ICmpInst(Pred, B, CI);
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if (isKnownPositive(B, DL))
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return new ICmpInst(Pred, A, CI);
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}
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if (*C == 0 && Pred == ICmpInst::ICMP_SGT) {
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SelectPatternResult SPR = matchSelectPattern(X, A, B);
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if (SPR.Flavor == SPF_SMIN) {
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if (isKnownPositive(A, DL))
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return new ICmpInst(Pred, B, Cmp.getOperand(1));
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if (isKnownPositive(B, DL))
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return new ICmpInst(Pred, A, Cmp.getOperand(1));
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}
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}
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// FIXME: Use m_APInt to allow folds for splat constants.
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ConstantInt *CI = dyn_cast<ConstantInt>(Cmp.getOperand(1));
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if (!CI)
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return nullptr;
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// The following transforms are only worth it if the only user of the subtract
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// is the icmp.
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@ -19,11 +19,7 @@ define i1 @smin(i32 %other) {
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define <2 x i1> @smin_vec(<2 x i32> %x, <2 x i32> %other) {
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; CHECK-LABEL: @smin_vec(
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; CHECK-NEXT: [[NOTNEG:%.*]] = and <2 x i32> %x, <i32 7, i32 7>
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; CHECK-NEXT: [[POSITIVE:%.*]] = or <2 x i32> [[NOTNEG]], <i32 1, i32 1>
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[POSITIVE]], %other
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; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[POSITIVE]], <2 x i32> %other
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; CHECK-NEXT: [[TEST:%.*]] = icmp sgt <2 x i32> [[SEL]], zeroinitializer
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; CHECK-NEXT: [[TEST:%.*]] = icmp sgt <2 x i32> %other, zeroinitializer
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; CHECK-NEXT: ret <2 x i1> [[TEST]]
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;
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%notneg = and <2 x i32> %x, <i32 7, i32 7>
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@ -48,16 +44,12 @@ define i1 @smin_commute(i32 %other) {
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define <2 x i1> @smin_commute_vec(<2 x i32> %x, <2 x i32> %other) {
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; CHECK-LABEL: @smin_commute_vec(
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; CHECK-NEXT: [[NOTNEG:%.*]] = and <2 x i32> %x, <i32 7, i32 7>
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; CHECK-NEXT: [[POSITIVE:%.*]] = or <2 x i32> [[NOTNEG]], <i32 1, i32 1>
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[POSITIVE]], %other
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; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[CMP]], <2 x i32> %other, <2 x i32> [[POSITIVE]]
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; CHECK-NEXT: [[TEST:%.*]] = icmp sgt <2 x i32> [[SEL]], zeroinitializer
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; CHECK-NEXT: [[TEST:%.*]] = icmp sgt <2 x i32> %other, zeroinitializer
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; CHECK-NEXT: ret <2 x i1> [[TEST]]
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;
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%notneg = and <2 x i32> %x, <i32 7, i32 7>
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%positive = or <2 x i32> %notneg, <i32 1, i32 1>
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%cmp = icmp slt <2 x i32> %positive, %other
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%cmp = icmp slt <2 x i32> %other, %positive
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%sel = select <2 x i1> %cmp, <2 x i32> %other, <2 x i32> %positive
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%test = icmp sgt <2 x i32> %sel, zeroinitializer
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ret <2 x i1> %test
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