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ARM and Thumb2 support for atomic MIN/MAX/UMIN/UMAX loads.
rdar://9326019 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130234 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
fea8fea583
commit
f7da8821b4
@ -609,6 +609,18 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i8, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i16, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i8, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i16, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i8, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i16, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i8, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i16, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
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// Since the libcalls include locking, fold in the fences
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setShouldFoldAtomicFences(true);
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}
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@ -5031,6 +5043,109 @@ ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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return BB;
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}
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MachineBasicBlock *
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ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned Size,
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bool signExtend,
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ARMCC::CondCodes Cond) const {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction *MF = BB->getParent();
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MachineFunction::iterator It = BB;
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++It;
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unsigned dest = MI->getOperand(0).getReg();
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unsigned ptr = MI->getOperand(1).getReg();
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unsigned incr = MI->getOperand(2).getReg();
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unsigned oldval = dest;
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DebugLoc dl = MI->getDebugLoc();
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bool isThumb2 = Subtarget->isThumb2();
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unsigned ldrOpc, strOpc, extendOpc;
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switch (Size) {
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default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
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case 1:
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ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
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strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
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extendOpc = isThumb2 ? ARM::t2SXTBr : ARM::SXTBr;
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break;
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case 2:
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ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
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strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
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extendOpc = isThumb2 ? ARM::t2SXTHr : ARM::SXTHr;
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break;
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case 4:
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ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
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strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
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extendOpc = 0;
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break;
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}
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MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MF->insert(It, loopMBB);
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MF->insert(It, exitMBB);
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// Transfer the remainder of BB and its successor edges to exitMBB.
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exitMBB->splice(exitMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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exitMBB->transferSuccessorsAndUpdatePHIs(BB);
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
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unsigned scratch2 = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
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// thisMBB:
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// ...
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// fallthrough --> loopMBB
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BB->addSuccessor(loopMBB);
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// loopMBB:
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// ldrex dest, ptr
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// (sign extend dest, if required)
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// cmp dest, incr
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// cmov.cond scratch2, dest, incr
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// strex scratch, scratch2, ptr
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// cmp scratch, #0
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// bne- loopMBB
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// fallthrough --> exitMBB
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BB = loopMBB;
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AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
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// Sign extend the value, if necessary.
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if (signExtend && extendOpc) {
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oldval = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
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AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval).addReg(dest));
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}
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// Build compare and cmov instructions.
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AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
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.addReg(oldval).addReg(incr));
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BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
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.addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR);
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AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
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.addReg(ptr));
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AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
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.addReg(scratch).addImm(0));
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BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
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.addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
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BB->addSuccessor(loopMBB);
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BB->addSuccessor(exitMBB);
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// exitMBB:
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// ...
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BB = exitMBB;
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MI->eraseFromParent(); // The instruction is gone now.
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return BB;
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}
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static
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MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
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for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
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@ -5162,6 +5277,34 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case ARM::ATOMIC_LOAD_SUB_I32:
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return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
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case ARM::ATOMIC_LOAD_MIN_I8:
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return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
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case ARM::ATOMIC_LOAD_MIN_I16:
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return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
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case ARM::ATOMIC_LOAD_MIN_I32:
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return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
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case ARM::ATOMIC_LOAD_MAX_I8:
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return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
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case ARM::ATOMIC_LOAD_MAX_I16:
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return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
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case ARM::ATOMIC_LOAD_MAX_I32:
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return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
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case ARM::ATOMIC_LOAD_UMIN_I8:
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return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
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case ARM::ATOMIC_LOAD_UMIN_I16:
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return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
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case ARM::ATOMIC_LOAD_UMIN_I32:
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return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
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case ARM::ATOMIC_LOAD_UMAX_I8:
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return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
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case ARM::ATOMIC_LOAD_UMAX_I16:
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return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
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case ARM::ATOMIC_LOAD_UMAX_I32:
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return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
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case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
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case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
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case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
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@ -484,6 +484,11 @@ namespace llvm {
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MachineBasicBlock *BB,
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unsigned Size,
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unsigned BinOpcode) const;
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MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned Size,
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bool signExtend,
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ARMCC::CondCodes Cond) const;
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bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
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};
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@ -3256,6 +3256,18 @@ let usesCustomInserter = 1 in {
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def ATOMIC_LOAD_NAND_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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[(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_MIN_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
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[(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
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def ATOMIC_LOAD_MAX_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
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[(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
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def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
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[(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
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def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
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[(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
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def ATOMIC_LOAD_ADD_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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[(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
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@ -3274,6 +3286,18 @@ let usesCustomInserter = 1 in {
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def ATOMIC_LOAD_NAND_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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[(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_MIN_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
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[(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
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def ATOMIC_LOAD_MAX_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
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[(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
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def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
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[(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
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def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
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[(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
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def ATOMIC_LOAD_ADD_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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[(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
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@ -3292,6 +3316,18 @@ let usesCustomInserter = 1 in {
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def ATOMIC_LOAD_NAND_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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[(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_MIN_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
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[(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
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def ATOMIC_LOAD_MAX_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
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[(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
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def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
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[(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
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def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
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[(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
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def ATOMIC_SWAP_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
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