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ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets.
This makes it more likely that we can use the 16-bit push and pop instructions on Thumb-2, saving around 4 bytes per function. Differential Revision: http://reviews.llvm.org/D9165 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235637 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1688,8 +1688,8 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
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for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
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unsigned Reg = UnspilledCS1GPRs[i];
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// Don't spill high register if the function is thumb1
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if (!AFI->isThumb1OnlyFunction() ||
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// Don't spill high register if the function is thumb
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if (!AFI->isThumbFunction() ||
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isARMLowRegister(Reg) || Reg == ARM::LR) {
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MRI.setPhysRegUsed(Reg);
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if (!MRI.isReserved(Reg))
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@ -33,7 +33,7 @@ define void @foo2(double %p0, ; --> D0
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%struct_t* byval %p10) ; --> Stack+8
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{
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entry:
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;CHECK: push.w {r11, lr}
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;CHECK: push {r7, lr}
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;CHECK-NOT: stm
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;CHECK: add r0, sp, #16
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;CHECK: bl fooUseStruct
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@ -22,7 +22,7 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP
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i32 %p3) #0 { ; --> SP+4, NSAA=SP+12
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entry:
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;CHECK: sub sp, #12
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;CHECK: push.w {r11, lr}
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;CHECK: push {r7, lr}
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;CHECK: sub sp, #4
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;CHECK: add r0, sp, #12
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;CHECK: str r2, [sp, #16]
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@ -19,7 +19,7 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP
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i32 %p2) #0 { ; --> SP+24, NSAA=SP+24
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entry:
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;CHECK: push.w {r11, lr}
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;CHECK: push {r7, lr}
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;CHECK: ldr r0, [sp, #32]
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;CHECK: bl fooUseI32
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call void @fooUseI32(i32 %p2)
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@ -264,14 +264,14 @@ declare void @_ZSt9terminatev()
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; CHECK-THUMB-V7-FP-LABEL: _Z4testiiiiiddddd:
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; CHECK-THUMB-V7-FP: .cfi_startproc
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; CHECK-THUMB-V7-FP: push.w {r4, r7, r11, lr}
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; CHECK-THUMB-V7-FP: push {r4, r6, r7, lr}
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; CHECK-THUMB-V7-FP: .cfi_def_cfa_offset 16
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; CHECK-THUMB-V7-FP: .cfi_offset lr, -4
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; CHECK-THUMB-V7-FP: .cfi_offset r11, -8
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; CHECK-THUMB-V7-FP: .cfi_offset r7, -12
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; CHECK-THUMB-V7-FP: .cfi_offset r7, -8
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; CHECK-THUMB-V7-FP: .cfi_offset r6, -12
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; CHECK-THUMB-V7-FP: .cfi_offset r4, -16
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; CHECK-THUMB-V7-FP: add r7, sp, #4
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; CHECK-THUMB-V7-FP: .cfi_def_cfa r7, 12
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; CHECK-THUMB-V7-FP: add r7, sp, #8
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; CHECK-THUMB-V7-FP: .cfi_def_cfa r7, 8
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; CHECK-THUMB-V7-FP: vpush {d8, d9, d10, d11, d12}
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; CHECK-THUMB-V7-FP: .cfi_offset d12, -24
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; CHECK-THUMB-V7-FP: .cfi_offset d11, -32
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@ -300,14 +300,14 @@ declare void @_ZSt9terminatev()
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; CHECK-THUMB-V7-FP-NOIAS-LABEL: _Z4testiiiiiddddd:
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; CHECK-THUMB-V7-FP-NOIAS: .cfi_startproc
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; CHECK-THUMB-V7-FP-NOIAS: push.w {r4, r7, r11, lr}
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; CHECK-THUMB-V7-FP-NOIAS: push {r4, r6, r7, lr}
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; CHECK-THUMB-V7-FP-NOIAS: .cfi_def_cfa_offset 16
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; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 14, -4
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; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 11, -8
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; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 7, -12
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; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 7, -8
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; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 6, -12
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; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 4, -16
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; CHECK-THUMB-V7-FP-NOIAS: add r7, sp, #4
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; CHECK-THUMB-V7-FP-NOIAS: .cfi_def_cfa 7, 12
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; CHECK-THUMB-V7-FP-NOIAS: add r7, sp, #8
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; CHECK-THUMB-V7-FP-NOIAS: .cfi_def_cfa 7, 8
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; CHECK-THUMB-V7-FP-NOIAS: vpush {d8, d9, d10, d11, d12}
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; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 268, -24
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; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 267, -32
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@ -404,11 +404,11 @@ entry:
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; CHECK-THUMB-V7-FP-ELIM-LABEL: test2:
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; CHECK-THUMB-V7-FP-ELIM: .cfi_startproc
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; CHECK-THUMB-V7-FP-ELIM: push.w {r11, lr}
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; CHECK-THUMB-V7-FP-ELIM: push {r7, lr}
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; CHECK-THUMB-V7-FP-ELIM: .cfi_def_cfa_offset 8
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; CHECK-THUMB-V7-FP-ELIM: .cfi_offset lr, -4
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; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r11, -8
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; CHECK-THUMB-V7-FP-ELIM: pop.w {r11, pc}
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; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r7, -8
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; CHECK-THUMB-V7-FP-ELIM: pop {r7, pc}
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; CHECK-THUMB-V7-FP-ELIM: .cfi_endproc
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@ -522,13 +522,13 @@ entry:
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; CHECK-THUMB-V7-FP-ELIM-LABEL: test3:
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; CHECK-THUMB-V7-FP-ELIM: .cfi_startproc
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; CHECK-THUMB-V7-FP-ELIM: push.w {r4, r5, r11, lr}
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; CHECK-THUMB-V7-FP-ELIM: push {r4, r5, r7, lr}
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; CHECK-THUMB-V7-FP-ELIM: .cfi_def_cfa_offset 16
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; CHECK-THUMB-V7-FP-ELIM: .cfi_offset lr, -4
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; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r11, -8
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; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r7, -8
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; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r5, -12
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; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r4, -16
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; CHECK-THUMB-V7-FP-ELIM: pop.w {r4, r5, r11, pc}
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; CHECK-THUMB-V7-FP-ELIM: pop {r4, r5, r7, pc}
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; CHECK-THUMB-V7-FP-ELIM: .cfi_endproc
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@ -12,11 +12,11 @@ declare void @bar(i8*)
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define void @check_simple() minsize {
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; CHECK-LABEL: check_simple:
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; CHECK: push.w {r7, r8, r9, r10, r11, lr}
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; CHECK: push {r3, r4, r5, r6, r7, lr}
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; CHECK-NOT: sub sp, sp,
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; ...
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; CHECK-NOT: add sp, sp,
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; CHECK: pop.w {r0, r1, r2, r3, r11, pc}
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; CHECK: pop {r0, r1, r2, r3, r7, pc}
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; CHECK-T1-LABEL: check_simple:
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; CHECK-T1: push {r3, r4, r5, r6, r7, lr}
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@ -44,11 +44,11 @@ define void @check_simple() minsize {
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define void @check_simple_too_big() minsize {
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; CHECK-LABEL: check_simple_too_big:
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; CHECK: push.w {r11, lr}
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; CHECK: push {r7, lr}
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; CHECK: sub sp,
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; ...
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; CHECK: add sp,
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; CHECK: pop.w {r11, pc}
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; CHECK: pop {r7, pc}
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%var = alloca i8, i32 64
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call void @bar(i8* %var)
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ret void
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@ -93,11 +93,11 @@ define void @check_vfp_fold() minsize {
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; folded in except that doing so would clobber the value being returned.
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define i64 @check_no_return_clobber() minsize {
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; CHECK-LABEL: check_no_return_clobber:
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; CHECK: push.w {r5, r6, r7, r8, r9, r10, r11, lr}
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; CHECK: push {r1, r2, r3, r4, r5, r6, r7, lr}
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; CHECK-NOT: sub sp,
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; ...
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; CHECK: add sp, #24
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; CHECK: pop.w {r11, pc}
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; CHECK: pop {r7, pc}
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; Just to keep iOS FileCheck within previous function:
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; CHECK-IOS-LABEL: check_no_return_clobber:
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@ -176,9 +176,9 @@ define void @test_varsize(...) minsize {
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; CHECK-LABEL: test_varsize:
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; CHECK: sub sp, #16
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; CHECK: push.w {r9, r10, r11, lr}
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; CHECK: push {r5, r6, r7, lr}
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; ...
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; CHECK: pop.w {r2, r3, r11, lr}
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; CHECK: pop.w {r2, r3, r7, lr}
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; CHECK: add sp, #16
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; CHECK: bx lr
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@ -35,7 +35,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" {
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; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to
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; appropriate sentinel so no special return needed).
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; CHECK-M-LABEL: irq_fn:
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; CHECK-M: push.w {r4, r10, r11, lr}
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; CHECK-M: push.w {r4, r7, r11, lr}
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; CHECK-M: add.w r11, sp, #8
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; CHECK-M: mov r4, sp
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; CHECK-M: bfc r4, #0, #3
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@ -43,7 +43,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" {
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; CHECK-M: bl _bar
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; CHECK-M: sub.w r4, r11, #8
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; CHECK-M: mov sp, r4
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; CHECK-M: pop.w {r4, r10, r11, pc}
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; CHECK-M: pop.w {r4, r7, r11, pc}
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call arm_aapcscc void @bar()
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ret void
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@ -7,8 +7,8 @@ entry:
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; CHECK-LABEL: __gcov_execlp:
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; CHECK: sub sp, #8
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; CHECK: push
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; CHECK: add r7, sp, #4
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; CHECK: sub.w r4, r7, #4
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; CHECK: add r7, sp, #8
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; CHECK: sub.w r4, r7, #8
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; CHECK: mov sp, r4
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; CHECK-NOT: mov sp, r7
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; CHECK: add sp, #8
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@ -29,7 +29,7 @@ define i32 @test3() {
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; DARWIN: sub.w sp, sp, #805306368
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; DARWIN: sub sp, #20
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; LINUX-LABEL: test3:
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; LINUX: push.w {r4, r7, r11, lr}
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; LINUX: push {r4, r6, r7, lr}
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; LINUX: sub.w sp, sp, #805306368
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; LINUX: sub sp, #16
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%retval = alloca i32, align 4
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@ -32,13 +32,13 @@ bb: ; preds = %entry
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; ELFOBJ: Section {
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; ELFOBJ: Name: .text
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; ELFOBJ-LE: SectionData (
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;;; BL __aeabi_read_tp is ---------+
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;;; V
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; ELFOBJ-LE-NEXT: 0000: 2DE90048 0E487844 0168FFF7 FEFF4058
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;;; BL __aeabi_read_tp is ---+
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;;; V
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; ELFOBJ-LE-NEXT: 0000: 80B50E48 78440168 FFF7FEFF 40580D28
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; ELFOBJ-BE: SectionData (
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;;; BL __aeabi_read_tp is ---------+
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;;; V
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; ELFOBJ-BE-NEXT: 0000: E92D4800 480E4478 6801F7FF FFFE5840
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;;; BL __aeabi_read_tp is ---+
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;;; V
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; ELFOBJ-BE-NEXT: 0000: B580480E 44786801 F7FFFFFE 5840280D
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bb1: ; preds = %entry
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@ -24,13 +24,13 @@ entry:
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; make sure that bl 0 <foo> (fff7feff) is correctly encoded
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; CHECK: Sections [
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; CHECK: SectionData (
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; CHECK: 0000: 70472DE9 0048FFF7 FEFFBDE8 0088
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; CHECK: 0000: 704780B5 FFF7FEFF 80BD
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; CHECK: )
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; CHECK: ]
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; CHECK: Relocations [
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; CHECK-NEXT: Section {{.*}} .rel.text {
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; CHECK-NEXT: 0x6 R_ARM_THM_CALL foo 0x0
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; CHECK-NEXT: 0x4 R_ARM_THM_CALL foo 0x0
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; CHECK-NEXT: }
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; CHECK-NEXT: Section {{.*}} .rel.ARM.exidx {
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; CHECK-NEXT: 0x0 R_ARM_PREL31 .text 0x0
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