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[ARM] Accept conditional versions of BXNS and BLXNS
These instructions end in "S" but are not flag-setting, so they need including in the list of special cases in the assembly parser. Differential Revision: http://reviews.llvm.org/D21077 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272015 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5420,6 +5420,7 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
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Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
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Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
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Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
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Mnemonic == "bxns" || Mnemonic == "blxns" ||
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(Mnemonic == "movs" && isThumb()))) {
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Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
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CarrySetting = true;
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@ -146,12 +146,26 @@ sg
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// CHECK: bxns r0 @ encoding: [0x04,0x47]
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bxns r0
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// UNDEF-BASELINE: error: invalid operand for instruction
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// UNDEF-BASELINE: error: conditional execution not supported in Thumb1
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// CHECK-MAINLINE: it eq @ encoding: [0x08,0xbf]
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// CHECK-MAINLINE: bxnseq r1 @ encoding: [0x0c,0x47]
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it eq
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bxnseq r1
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// CHECK: bxns lr @ encoding: [0x74,0x47]
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bxns lr
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// CHECK: blxns r0 @ encoding: [0x84,0x47]
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blxns r0
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// UNDEF-BASELINE: error: invalid operand for instruction
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// UNDEF-BASELINE: error: conditional execution not supported in Thumb1
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// CHECK-MAINLINE: it eq @ encoding: [0x08,0xbf]
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// CHECK-MAINLINE: blxnseq r1 @ encoding: [0x8c,0x47]
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it eq
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blxnseq r1
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// CHECK: tt r0, r1 @ encoding: [0x41,0xe8,0x00,0xf0]
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tt r0, r1
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