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Rename UpdateRegAllocHint to match style guidelines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230357 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -694,13 +694,13 @@ public:
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return false;
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}
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/// UpdateRegAllocHint - A callback to allow target a chance to update
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/// updateRegAllocHint - A callback to allow target a chance to update
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/// register allocation hints when a register is "changed" (e.g. coalesced)
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/// to another register. e.g. On ARM, some virtual registers should target
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/// register pairs, if one of pair is coalesced to another register, the
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/// allocation hint of the other half of the pair should be changed to point
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/// to the new register.
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virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
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virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg,
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MachineFunction &MF) const {
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// Do nothing.
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}
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@ -1393,7 +1393,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
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LIS->removeInterval(CP.getSrcReg());
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// Update regalloc hint.
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TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
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TRI->updateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
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DEBUG({
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dbgs() << "\tSuccess: " << PrintReg(CP.getSrcReg(), TRI, CP.getSrcIdx())
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@ -264,7 +264,7 @@ ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
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}
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void
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ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
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ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg,
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MachineFunction &MF) const {
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
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@ -135,7 +135,7 @@ public:
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const MachineFunction &MF,
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const VirtRegMap *VRM) const override;
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void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
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void updateRegAllocHint(unsigned Reg, unsigned NewReg,
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MachineFunction &MF) const override;
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bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const override;
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