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Rename UpdateRegAllocHint to match style guidelines.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230357 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2015-02-24 19:10:57 +00:00
parent dd1a6e074d
commit f8c57a105e
4 changed files with 5 additions and 5 deletions
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4
include/llvm/Target/TargetRegisterInfo.h
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@ -694,13 +694,13 @@ public:
return false; return false;
} }
/// UpdateRegAllocHint - A callback to allow target a chance to update /// updateRegAllocHint - A callback to allow target a chance to update
/// register allocation hints when a register is "changed" (e.g. coalesced) /// register allocation hints when a register is "changed" (e.g. coalesced)
/// to another register. e.g. On ARM, some virtual registers should target /// to another register. e.g. On ARM, some virtual registers should target
/// register pairs, if one of pair is coalesced to another register, the /// register pairs, if one of pair is coalesced to another register, the
/// allocation hint of the other half of the pair should be changed to point /// allocation hint of the other half of the pair should be changed to point
/// to the new register. /// to the new register.
virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg,
MachineFunction &MF) const { MachineFunction &MF) const {
// Do nothing. // Do nothing.
} }

2
lib/CodeGen/RegisterCoalescer.cpp
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@ -1393,7 +1393,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
LIS->removeInterval(CP.getSrcReg()); LIS->removeInterval(CP.getSrcReg());
// Update regalloc hint. // Update regalloc hint.
TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF); TRI->updateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
DEBUG({ DEBUG({
dbgs() << "\tSuccess: " << PrintReg(CP.getSrcReg(), TRI, CP.getSrcIdx()) dbgs() << "\tSuccess: " << PrintReg(CP.getSrcReg(), TRI, CP.getSrcIdx())

2
lib/Target/ARM/ARMBaseRegisterInfo.cpp
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@ -264,7 +264,7 @@ ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
} }
void void
ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg,
MachineFunction &MF) const { MachineFunction &MF) const {
MachineRegisterInfo *MRI = &MF.getRegInfo(); MachineRegisterInfo *MRI = &MF.getRegInfo();
std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);

2
lib/Target/ARM/ARMBaseRegisterInfo.h
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@ -135,7 +135,7 @@ public:
const MachineFunction &MF, const MachineFunction &MF,
const VirtRegMap *VRM) const override; const VirtRegMap *VRM) const override;
void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, void updateRegAllocHint(unsigned Reg, unsigned NewReg,
MachineFunction &MF) const override; MachineFunction &MF) const override;
bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const override; bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const override;