From f90a656a9fbbbf451d0022420e99aee6d3810e93 Mon Sep 17 00:00:00 2001
From: Misha Brukman <brukman+llvm@gmail.com>
Date: Mon, 27 Sep 2004 18:22:18 +0000
Subject: [PATCH] SparcV8 int regs are not only 32-bits in width, but they are
 32-bit aligned!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16526 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Sparc/SparcRegisterInfo.td     | 2 +-
 lib/Target/SparcV8/SparcV8RegisterInfo.td | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td
index 728c115f861..b3d202bf26f 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/lib/Target/Sparc/SparcRegisterInfo.td
@@ -23,7 +23,7 @@ include "../SparcRegisterInfo.td"
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<i32, 64, [L0, L1, L2, L3, L4, L5, L6, L7,
+def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5,
                                      G1, G2, G3, G4, G5, G6, G7,
                                      O0, O1, O2, O3, O4, O5, O7,
diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.td b/lib/Target/SparcV8/SparcV8RegisterInfo.td
index 728c115f861..b3d202bf26f 100644
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.td
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.td
@@ -23,7 +23,7 @@ include "../SparcRegisterInfo.td"
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<i32, 64, [L0, L1, L2, L3, L4, L5, L6, L7,
+def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5,
                                      G1, G2, G3, G4, G5, G6, G7,
                                      O0, O1, O2, O3, O4, O5, O7,