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Represent NEON load/store alignments in bytes, not bits.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107701 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-07-06 21:26:18 +00:00
parent 5ee99923c1
commit f967ca0eaf
3 changed files with 13 additions and 7 deletions
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2
lib/Target/ARM/ARMAddressingModes.h
View File

@ -520,6 +520,8 @@ namespace ARM_AM {
// This is stored in two operands [regaddr, align]. The first is the
// address register. The second operand is the value of the alignment
// specifier to use or zero if no explicit alignment.
// Valid alignments are: 0, 8, 16, and 32 bytes, depending on the specific
// instruction.
} // end namespace ARM_AM
} // end namespace llvm

12
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -832,7 +832,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
// FIXME: Neon instructions should support predicates
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
.addFrameIndex(FI).addImm(128)
.addFrameIndex(FI).addImm(16)
.addReg(SrcReg, getKillRegState(isKill))
.addMemOperand(MMO));
} else {
@ -849,7 +849,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
// FIXME: It's possible to only store part of the QQ register if the
// spilled def has a sub-register index.
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32))
.addFrameIndex(FI).addImm(128);
.addFrameIndex(FI).addImm(16);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
@ -929,7 +929,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
case ARM::QPR_8RegClassID:
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
.addFrameIndex(FI).addImm(128)
.addFrameIndex(FI).addImm(16)
.addMemOperand(MMO));
} else {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
@ -946,7 +946,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
AddDefaultPred(MIB.addFrameIndex(FI).addImm(16).addMemOperand(MMO));
} else {
MachineInstrBuilder MIB =
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
@ -1131,7 +1131,7 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
if (MFI.getObjectAlignment(FI) >= 16 &&
getRegisterInfo().canRealignStack(MF)) {
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VST1q))
.addFrameIndex(FI).addImm(128)
.addFrameIndex(FI).addImm(16)
.addReg(SrcReg,
getKillRegState(isKill) | getUndefRegState(isUndef),
SrcSubReg)
@ -1157,7 +1157,7 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
getDeadRegState(isDead) |
getUndefRegState(isUndef),
DstSubReg)
.addFrameIndex(FI).addImm(128).addImm(Pred).addReg(PredReg);
.addFrameIndex(FI).addImm(16).addImm(Pred).addReg(PredReg);
} else {
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDMQ))
.addReg(DstReg,

6
lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
View File

@ -602,8 +602,12 @@ void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op,
O << "[" << getRegisterName(MO1.getReg());
if (MO2.getImm()) {
unsigned Align = MO2.getImm();
assert((Align == 8 || Align == 16 || Align == 32) &&
"unexpected NEON load/store alignment");
Align <<= 3;
// FIXME: Both darwin as and GNU as violate ARM docs here.
O << ", :" << MO2.getImm();
O << ", :" << Align;
}
O << "]";
}