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ARM branch relaxation for unconditional t1 branches.

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rdar://11059157

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153055 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2012-03-19 21:32:32 +00:00
parent ceee984302
commit fa1f74470a
1 changed files with 11 additions and 0 deletions
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11
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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@ -167,6 +167,7 @@ static unsigned getRelaxedOpcode(unsigned Op) {
case ARM::tBcc: return ARM::t2Bcc;
case ARM::tLDRpciASM: return ARM::t2LDRpci;
case ARM::tADR: return ARM::t2ADR;
case ARM::tB: return ARM::t2B;
}
}
@ -181,6 +182,16 @@ bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
const MCInstFragment *DF,
const MCAsmLayout &Layout) const {
switch ((unsigned)Fixup.getKind()) {
case ARM::fixup_arm_thumb_br: {
// Relaxing tB to t2B. tB has a signed 12-bit displacement with the
// low bit being an implied zero. There's an implied +4 offset for the
// branch, so we adjust the other way here to determine what's
// encodable.
//
// Relax if the value is too big for a (signed) i8.
int64_t Offset = int64_t(Value) - 4;
return Offset > 2046 || Offset < -2048;
}
case ARM::fixup_arm_thumb_bcc: {
// Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
// low bit being an implied zero. There's an implied +4 offset for the