From fa458d8ad29a9f81f0ec96ebeca74434c30f1cd1 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Tue, 21 Jan 2014 13:22:08 +0000 Subject: [PATCH] [mips][sched] Renamed II_FdivSingle and II_FdivDouble to II_DIV_S and II_DIV_D respectively No functional change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199738 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMipsInstrFPU.td | 4 ++-- lib/Target/Mips/MipsInstrFPU.td | 4 ++-- lib/Target/Mips/MipsSchedule.td | 8 ++++---- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/lib/Target/Mips/MicroMipsInstrFPU.td b/lib/Target/Mips/MicroMipsInstrFPU.td index 65adb60b075..39573216097 100644 --- a/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/lib/Target/Mips/MicroMipsInstrFPU.td @@ -1,7 +1,7 @@ let isCodeGenOnly = 1, Predicates = [InMicroMips] in { def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, ADDS_FM_MM<0, 0x30>; -def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>, +def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, ADDS_FM_MM<0, 0xf0>; def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, ADDS_FM_MM<0, 0xb0>; @@ -10,7 +10,7 @@ def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>, ADDS_FM_MM<1, 0x30>; -def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, IIFdivDouble, 0, fdiv>, +def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>, ADDS_FM_MM<1, 0xf0>; def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>, ADDS_FM_MM<1, 0xb0>; diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 796f6890c31..cb14815c38c 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -422,9 +422,9 @@ let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace="Mips64" in { def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, ADDS_FM<0x00, 16>; defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>; -def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>, +def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, ADDS_FM<0x03, 16>; -defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>; +defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>; def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, ADDS_FM<0x02, 16>; defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>; diff --git a/lib/Target/Mips/MipsSchedule.td b/lib/Target/Mips/MipsSchedule.td index 1c23a7660af..f7d7ee74b5f 100644 --- a/lib/Target/Mips/MipsSchedule.td +++ b/lib/Target/Mips/MipsSchedule.td @@ -20,8 +20,6 @@ def IIAlu : InstrItinClass; def IILoad : InstrItinClass; def IIStore : InstrItinClass; def IIBranch : InstrItinClass; -def IIFdivSingle : InstrItinClass; -def IIFdivDouble : InstrItinClass; def IIFsqrtSingle : InstrItinClass; def IIFsqrtDouble : InstrItinClass; def IIFrecipFsqrtStep : InstrItinClass; @@ -52,6 +50,8 @@ def II_DDIV : InstrItinClass; def II_DDIVU : InstrItinClass; def II_DIV : InstrItinClass; def II_DIVU : InstrItinClass; +def II_DIV_D : InstrItinClass; +def II_DIV_S : InstrItinClass; def II_DMULT : InstrItinClass; def II_DMULTU : InstrItinClass; def II_DROTR : InstrItinClass; @@ -225,8 +225,8 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData]>, InstrItinData]>, InstrItinData]>, - InstrItinData]>, - InstrItinData]>, + InstrItinData]>, + InstrItinData]>, InstrItinData]>, InstrItinData]>, InstrItinData]>,