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Fix SHL_PARTS

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Start implementation of integer varargs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21065 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-04-03 22:13:27 +00:00
parent 63b720ac7c
commit fa55470e39
1 changed files with 10 additions and 2 deletions
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12
lib/Target/PowerPC/PPCISelPattern.cpp
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@ -192,8 +192,16 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
// If the function takes variable number of arguments, make a frame index for
// the start of the first vararg value... for expansion of llvm.va_start.
if (F.isVarArg())
if (F.isVarArg()) {
VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
// If this function is vararg, store r4-r10 to their spots on the stack so
// that they may be loaded by dereferencing va_next
SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
SDOperand Val = DAG.getCopyFromReg(PPC::R4, MVT::i32, DAG.getRoot());
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val, Val, FIN);
DAG.setRoot(Val.getValue(1));
ArgValues.push_back(Store);
}
return ArgValues;
}
@ -1352,7 +1360,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
BuildMI(BB, PPC::SRW, 2, Tmp3).addReg(ShiftOpLo).addReg(Tmp1);
BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
BuildMI(BB, PPC::ADDI, 2, Tmp5).addReg(SHReg).addSImm(-32);
BuildMI(BB, PPC::SLW, 2, Tmp6).addReg(ShiftOpHi).addReg(Tmp5);
BuildMI(BB, PPC::SLW, 2, Tmp6).addReg(ShiftOpLo).addReg(Tmp5);
BuildMI(BB, PPC::OR, 2, Result+1).addReg(Tmp4).addReg(Tmp6);
BuildMI(BB, PPC::SLW, 2, Result).addReg(ShiftOpLo).addReg(SHReg);
} else if (ISD::SRL_PARTS == opcode) {