From fa6f30947b6fe9c55dad3c720afbaa2974b2defe Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 6 Feb 2004 06:04:25 +0000 Subject: [PATCH] Syntax hilight examples and add note about emacs/vim mode files git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11146 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/TableGenFundamentals.html | 107 ++++++++++++++++++--------------- 1 file changed, 57 insertions(+), 50 deletions(-) diff --git a/docs/TableGenFundamentals.html b/docs/TableGenFundamentals.html index f402361b0bc..c57cda26ebe 100644 --- a/docs/TableGenFundamentals.html +++ b/docs/TableGenFundamentals.html @@ -38,11 +38,11 @@
  • TableGen backends
      • -
    1. x
      2. +
    2. todo
  • The LLVM code generator
      • -
    1. x
      2. +
    2. todo
    @@ -65,6 +65,12 @@ href="#backends">TableGen backend" for processing. The current major user of TableGen is the LLVM code generator.

    +

    +Note that if you work on TableGen much, and use emacs or vim, that you can find +an emacs "TableGen mode" and a vim language file in llvm/utils/emacs +and llvm/utils/vim directory of your LLVM distribution, respectively. +

    + @@ -124,27 +130,27 @@ prints this (at the time of this writing): 

     ...
-def ADDrr8 {    // Instruction X86Inst I2A8 Pattern
-  string Name = "add";
-  string Namespace = "X86";
-  list<Register> Uses = [];
-  list<Register> Defs = [];
-  bit isReturn = 0;
-  bit isBranch = 0;
-  bit isCall = 0;
-  bit isTwoAddress = 1;
-  bit isTerminator = 0;
-  dag Pattern = (set R8, (plus R8, R8));
-  bits<8> Opcode = { 0, 0, 0, 0, 0, 0, 0, 0 };
+def ADDrr8 {    // Instruction X86Inst I2A8 Pattern
+  string Name = "add";
+  string Namespace = "X86";
+  list<Register> Uses = [];
+  list<Register> Defs = [];
+  bit isReturn = 0;
+  bit isBranch = 0;
+  bit isCall = 0;
+  bit isTwoAddress = 1;
+  bit isTerminator = 0;
+  dag Pattern = (set R8, (plus R8, R8));
+  bits<8> Opcode = { 0, 0, 0, 0, 0, 0, 0, 0 };
   Format Form = MRMDestReg;
-  bits<5> FormBits = { 0, 0, 0, 1, 1 };
+  bits<5> FormBits = { 0, 0, 0, 1, 1 };
   ArgType Type = Arg8;
-  bits<3> TypeBits = { 0, 0, 1 };
-  bit hasOpSizePrefix = 0;
-  bit printImplicitUses = 0;
-  bits<4> Prefix = { 0, 0, 0, 0 };
+  bits<3> TypeBits = { 0, 0, 1 };
+  bit hasOpSizePrefix = 0;
+  bit printImplicitUses = 0;
+  bits<4> Prefix = { 0, 0, 0, 0 };
   FPFormat FPForm = ?;
-  bits<3> FPFormBits = { 0, 0, 0 };
+  bits<3> FPFormBits = { 0, 0, 0 };
 }
 ...

    @@ -169,7 +175,7 @@ TableGen, all of the information was derived from the following definition: 

    -def ADDrr8   : I2A8<"add", 0x00, MRMDestReg>,
+def ADDrr8   : I2A8<"add", 0x00, MRMDestReg>,
                Pattern<(set R8, (plus R8, R8))>;

    @@ -284,32 +290,33 @@ TableGen types are:

    @@ -386,10 +393,10 @@ file: 

    -class C { bit V = 1; }
-def X : C;
-def Y : C {
-  string Greeting = "hello";
+class C { bit V = 1; }
+def X : C;
+def Y : C {
+  string Greeting = "hello";
 }

    @@ -431,8 +438,8 @@ value for example, a new class could be added to the example above, redefining the V field for all of its subclasses:

    -class D : C { let V = 0; }
-def Z : D;
+class D : C { let V = 0; }
+def Z : D;

    @@ -472,7 +479,7 @@ specified as a double quoted string immediately after the 'include' keyword. Example: 

    -  include "foo.td"
+  include "foo.td"

    @@ -497,15 +504,15 @@ and one of more records to bind the values in. Here are some examples: 

    -let isTerminator = 1, isReturn = 1 in
-  def RET : X86Inst<"ret", 0xC3, RawFrm, NoArg>;
+let isTerminator = 1, isReturn = 1 in
+  def RET : X86Inst<"ret", 0xC3, RawFrm, NoArg>;
 
-let isCall = 1 in
-  // All calls clobber the non-callee saved registers...
-  let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
-    def CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoArg>;
-    def CALLr32     : X86Inst<"call", 0xFF, MRMS2r, Arg32>;
-    def CALLm32     : X86Inst<"call", 0xFF, MRMS2m, Arg32>;
+let isCall = 1 in
+  // All calls clobber the non-callee saved registers...
+  let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
+    def CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoArg>;
+    def CALLr32     : X86Inst<"call", 0xFF, MRMS2r, Arg32>;
+    def CALLm32     : X86Inst<"call", 0xFF, MRMS2m, Arg32>;
   }