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[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Artyom Skrobov 2013-11-08 16:16:30 +00:00
parent 62ab26548f
commit fa840ba402
3 changed files with 59 additions and 9 deletions
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23
lib/Target/ARM/ARMInstrInfo.td
View File

@ -4676,7 +4676,8 @@ def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
[(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
imm:$CRm, imm:$opc2)]> {
imm:$CRm, imm:$opc2)]>,
Requires<[PreV8]> {
bits<4> opc1;
bits<4> CRn;
bits<4> CRd;
@ -4697,7 +4698,8 @@ def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
[(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
imm:$CRm, imm:$opc2)]> {
imm:$CRm, imm:$opc2)]>,
Requires<[PreV8]> {
let Inst{31-28} = 0b1111;
bits<4> opc1;
bits<4> CRn;
@ -4875,10 +4877,10 @@ defm LDC : LdStCop <1, 0, "ldc">;
defm LDCL : LdStCop <1, 1, "ldcl">;
defm STC : LdStCop <0, 0, "stc">;
defm STCL : LdStCop <0, 1, "stcl">;
defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
defm STC2 : LdSt2Cop<0, 0, "stc2">;
defm STC2L : LdSt2Cop<0, 1, "stc2l">;
defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
//===----------------------------------------------------------------------===//
// Move between coprocessor and ARM core register.
@ -4955,14 +4957,16 @@ def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
(ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
c_imm:$CRm, imm0_7:$opc2),
[(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
imm:$CRm, imm:$opc2)]>;
imm:$CRm, imm:$opc2)]>,
Requires<[PreV8]>;
def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
(MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
c_imm:$CRm, 0)>;
def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
(outs GPRwithAPSR:$Rt),
(ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
imm0_7:$opc2), []>;
imm0_7:$opc2), []>,
Requires<[PreV8]>;
def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
(MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
c_imm:$CRm, 0)>;
@ -4999,7 +5003,8 @@ def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
: ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
Requires<[PreV8]> {
let Inst{31-28} = 0b1111;
let Inst{23-21} = 0b010;
let Inst{20} = direction;

10
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -1363,6 +1363,11 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
break;
}
uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
.getFeatureBits();
if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(coproc));
Inst.addOperand(MCOperand::CreateImm(CRd));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
@ -3814,6 +3819,11 @@ static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
if (Val == 0xA || Val == 0xB)
return MCDisassembler::Fail;
uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
.getFeatureBits();
if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Val));
return MCDisassembler::Success;
}

35
test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt
View File

@ -21,3 +21,38 @@
0x05 0xf0 0x20 0xe3
# CHECK: sevl
# These are the only coprocessor instructions that remain defined in ARMv8
# (The operations on p10/p11 disassemble into FP/NEON instructions)
0x10 0x0e 0x00 0xee
# CHECK: mcr p14
0x10 0x0f 0x00 0xee
# CHECK: mcr p15
0x10 0x0e 0x10 0xee
# CHECK: mrc p14
0x10 0x0f 0x10 0xee
# CHECK: mrc p15
0x00 0x0e 0x40 0xec
# CHECK: mcrr p14
0x00 0x0f 0x40 0xec
# CHECK: mcrr p15
0x00 0x0e 0x50 0xec
# CHECK: mrrc p14
0x00 0x0f 0x50 0xec
# CHECK: mrrc p15
0x00 0x0e 0x80 0xec
# CHECK: stc p14
0x00 0x0e 0x90 0xec
# CHECK: ldc p14