mirror of
https://github.com/RPCSX/llvm.git
synced 2024-11-25 12:50:00 +00:00
Remove use of OpSize for populating VEX_PP field. A prefix encoding is now used instead. Simplify some other code. No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199353 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
da47fb533a
commit
fab01c1908
@ -634,7 +634,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
|
||||
unsigned char VEX_W = 0;
|
||||
|
||||
// XOP: Use XOP prefix byte 0x8f instead of VEX.
|
||||
bool XOP = false;
|
||||
bool XOP = (TSFlags >> X86II::VEXShift) & X86II::XOP;
|
||||
|
||||
// VEX_5M (VEX m-mmmmm field):
|
||||
//
|
||||
@ -688,16 +688,9 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
|
||||
|
||||
bool EncodeRC = false;
|
||||
|
||||
// Encode the operand size opcode prefix as needed.
|
||||
if (TSFlags & X86II::OpSize)
|
||||
VEX_PP = 0x01;
|
||||
|
||||
if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
|
||||
VEX_W = 1;
|
||||
|
||||
if ((TSFlags >> X86II::VEXShift) & X86II::XOP)
|
||||
XOP = true;
|
||||
|
||||
if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
|
||||
VEX_L = 1;
|
||||
if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2))
|
||||
@ -780,6 +773,9 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
|
||||
++CurOp;
|
||||
|
||||
switch (TSFlags & X86II::FormMask) {
|
||||
default: llvm_unreachable("Unexpected form in EmitVEXOpcodePrefix!");
|
||||
case X86II::RawFrm:
|
||||
break;
|
||||
case X86II::MRMDestMem: {
|
||||
// MRMDestMem instructions forms:
|
||||
// MemAddr, src1(ModR/M)
|
||||
@ -978,8 +974,6 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
|
||||
if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
|
||||
VEX_X = 0x0;
|
||||
break;
|
||||
default: // RawFrm
|
||||
break;
|
||||
}
|
||||
|
||||
// Emit segment override opcode prefix as needed.
|
||||
|
@ -834,7 +834,7 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
|
||||
unsigned char VEX_W = 0;
|
||||
|
||||
// XOP: Use XOP prefix byte 0x8f instead of VEX.
|
||||
bool XOP = false;
|
||||
bool XOP = (TSFlags >> X86II::VEXShift) & X86II::XOP;
|
||||
|
||||
// VEX_5M (VEX m-mmmmm field):
|
||||
//
|
||||
@ -869,16 +869,9 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
|
||||
//
|
||||
unsigned char VEX_PP = 0;
|
||||
|
||||
// Encode the operand size opcode prefix as needed.
|
||||
if (TSFlags & X86II::OpSize)
|
||||
VEX_PP = 0x01;
|
||||
|
||||
if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
|
||||
VEX_W = 1;
|
||||
|
||||
if ((TSFlags >> X86II::VEXShift) & X86II::XOP)
|
||||
XOP = true;
|
||||
|
||||
if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
|
||||
VEX_L = 1;
|
||||
|
||||
@ -946,6 +939,9 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
|
||||
}
|
||||
|
||||
switch (TSFlags & X86II::FormMask) {
|
||||
default: llvm_unreachable("Unexpected form in emitVEXOpcodePrefix!");
|
||||
case X86II::RawFrm:
|
||||
break;
|
||||
case X86II::MRMDestMem: {
|
||||
// MRMDestMem instructions forms:
|
||||
// MemAddr, src1(ModR/M)
|
||||
@ -1062,8 +1058,6 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
|
||||
if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
|
||||
VEX_B = 0x0;
|
||||
break;
|
||||
default: // RawFrm
|
||||
break;
|
||||
}
|
||||
|
||||
// Emit segment override opcode prefix as needed.
|
||||
|
Loading…
Reference in New Issue
Block a user