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Get rid of more dead code.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77227 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-07-27 18:38:54 +00:00
parent e91ea06dff
commit fc17fb0aee
5 changed files with 1 additions and 9 deletions
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2
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -165,9 +165,7 @@ namespace ARMII {
ADDri,
ADDrs,
ADDrr,
LDRri,
MOVr,
STRri,
SUBri,
SUBrs,
SUBrr

2
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -1368,7 +1368,7 @@ static bool isCSRestore(MachineInstr *MI,
void ARMBaseRegisterInfo::
emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
assert(!STI.isThumb1Only &&
assert(!STI.isThumb1Only() &&
"This emitEpilogue should not be executed for Thumb1!");
MachineBasicBlock::iterator MBBI = prior(MBB.end());

2
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -68,9 +68,7 @@ getOpcode(ARMII::Op Op) const {
case ARMII::ADDri: return ARM::ADDri;
case ARMII::ADDrs: return ARM::ADDrs;
case ARMII::ADDrr: return ARM::ADDrr;
case ARMII::LDRri: return 0;
case ARMII::MOVr: return ARM::MOVr;
case ARMII::STRri: return 0;
case ARMII::SUBri: return ARM::SUBri;
case ARMII::SUBrs: return ARM::SUBrs;
case ARMII::SUBrr: return ARM::SUBrr;

2
lib/Target/ARM/Thumb1InstrInfo.cpp
View File

@ -35,9 +35,7 @@ unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const {
case ARMII::ADDri: return ARM::tADDi8;
case ARMII::ADDrs: return 0;
case ARMII::ADDrr: return ARM::tADDrr;
case ARMII::LDRri: return 0;
case ARMII::MOVr: return ARM::tMOVr;
case ARMII::STRri: return 0;
case ARMII::SUBri: return ARM::tSUBi8;
case ARMII::SUBrs: return 0;
case ARMII::SUBrr: return ARM::tSUBrr;

2
lib/Target/ARM/Thumb2InstrInfo.cpp
View File

@ -36,9 +36,7 @@ unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const {
case ARMII::ADDri: return ARM::t2ADDri;
case ARMII::ADDrs: return ARM::t2ADDrs;
case ARMII::ADDrr: return ARM::t2ADDrr;
case ARMII::LDRri: return ARM::t2LDRi12;
case ARMII::MOVr: return ARM::t2MOVr;
case ARMII::STRri: return ARM::t2STRi12;
case ARMII::SUBri: return ARM::t2SUBri;
case ARMII::SUBrs: return ARM::t2SUBrs;
case ARMII::SUBrr: return ARM::t2SUBrr;